Contents
18 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
207 Modified Table136 “Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F)”
[renamed heading and bit name].
208 Modified Table138 “TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624)”
[renamed from TX FIFO Number of Frames Removed Ports 3 - 0].
209 Modified Table 139 “TX FIFO Errored Frame D rop Counter Ports 0 - 3 ($0x625 – 0x629 )” [renamed
from TX FIFO Number of Dropped Pa ckets Ports 0-3 and text unde r the description].
210 Modified Table 141 “TX FIFO Port Drop E nable ($0x63D)” [changed description for bits 3:0].
211 Modified T able142 “MDIO Single Command ($0x680)” [changed default; changed description and
default for bits 9:8; chan ged default for bits 4:0].
212 Modified Table 144 “Autoscan PHY Addr ess Enable ($0x682)” [add ed note to register descrip tion].
213 Modified Table146 “SPI3 Transmit and Global Configuration ($0x70 0)” [broke out bits 19:16, 7:4,
and 3:0 and changed descrip tion text].
215 Modified Table 147 “SPI3 Receive Con figuration ($0x701)” [brok e out bits and modified all text
adding SPHY and MPHY m odes].
221 Modified Table152 “Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)” [deleted
second paragraph of th e Register Description; re named bits to match caption ; changed text under
Description].
222 Added note under Secti on 8.4.11, “Optical Module Regi ster Overview”.
222 Modified Table153 “Optical Module Status Ports 0-3 ($0x799)” [edited register description].
222 Modified Table 154 “Optical Module Co ntrol Ports 0 - 3 ($0x79A)” [changed register descrip tion].
NA Removed/Res erved Table 190 “TX and RX AC/DC Co upling Selection ($7x780 )”.
NA Deleted old Figure 19, “ Typical GBIC Module Functional Diagram” under Section 5.7, “Optical
Module Interface”.
NA Removed old Section 5.1.1.5, “Pause Command Frames.”
180(old) Removed old Table 13. TX FIFO Mini Frame S ize for MAC and Pa dd in g Ena bl e Por t 0 t o 3 Re gi st er
(Addr: 0x63E) and replac ed with Reserved.
Revision Number: 006
Revision Date: Augus t 21, 2003
(Sheet 1 of 2)
Page# Description
19 Modified Table1 “Intel® IXF1104 Signal Descriptions”
53 Modified Section 5.1.1.1, “Padding of Undersized Frames on Transmit”.
60 Modified text for etherS tatsCollision in Table9 “RMON Additional Statistics”.
87 Modified Table 17 “Intel® IXF1104-to-Optical Module Interface Connections”
65 Modified first paragraph under Section 5.3.1.2, “Clock Rates”.
87 Modified Section 5.8.2.1, “H igh-Speed Serial Interface”.
100 Modified Figure 27 “Microprocessor — External and Internal Con nections”.
110 Changed PECL to LVDS under Section 6.1, “DC Specifications”.
113 Modified table no te 4 in Table32 “SPI3 Receive Interface Sig nal Parameters”.
119 Modified Table 37 “SerDes Timing Parame t er s” .
125 Modified Table 40 “Microprocess or Int er f ac e Wr ite Cy cl e A C Si gn al Pa ram e t ers ”.
Revision Number: 007
Revision Date: March 2 4, 2004
(Sheet 5 of 5)
Page # Description