Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller

When the CRC Error Pass Filter bit = 0 (“RX Packet Filter Control ($ Port_Index + 0x19)”), it takes precedence over the other filter bits. Any packet (Pause, Unicast, Multicast or Broadcast packet) with a CRC error will be marked as a bad frame when the CRC Error Pass Filter bit = 0.

Table 22. CRC Errored Packets Drop Enable Behavior

CRC Error

RX FIFO Errored-

RERR

 

 

Frame Drop

3

Actions

Pass

1

Enable

 

Enable2

 

 

 

 

 

 

 

 

 

 

 

 

 

When CRC Errored PASS = 1, CRC errored packets

1

 

x

x

 

are not filtered and are passed to the SPI3 interface.

 

 

They are not marked as bad, cannot be dropped, and

 

 

 

 

 

 

 

 

 

 

cannot be signaled with RERR.

 

 

 

 

 

 

 

 

 

 

 

Packets are marked as bad but not dropped in the

0

 

0

1

 

RX FIFO. These packets are sent to the SPI3

 

 

interface, and are signaled with an RERR to the

 

 

 

 

 

 

 

 

 

 

switch or Network Processor.

 

 

 

 

 

 

 

 

 

 

 

Packets are marked as bad but not dropped in the

0

 

0

0

 

RX FIFO. These packets are sent to the SPI3

 

 

 

 

 

interface, and are not signaled with an RERR.

 

 

 

 

 

 

 

 

 

 

 

CRC errored packets are marked as bad, dropped in

 

 

 

 

 

the RX FIFO, and never appear at the SPI3 interface.

0

 

1

x

 

NOTE: Packet sizes above the RX FIFO Transfer

 

 

Threshold (see Table 128 through Table 131)

 

 

 

 

 

cannot be dropped in the RX FIFO and are

 

 

 

 

 

passed to the SPI3 interface. These packets

 

 

 

 

 

can optionally be signaled with RERR on the

 

 

 

 

 

SPI3 interface if the RERR Enable bit = 1.

 

 

 

 

 

 

1. See Table 91 “RX Packet Filter Control ($ Port_Index + 0x19)” on page 172.

2. See Table 123 “RX FIFO Errored Frame Drop Enable ($0x59F)” on page 196.

3. See Table 147 “SPI3 Receive Configuration ($0x701)” on page 215. NOTE: x = “DON’T CARE”

5.1.1.4CRC Error Detection

Frames received by the MAC are checked for a correct CRC. When an incorrect CRC is detected on a received frame, the RX FCSError RMON statistic counter is incremented for each CRC errored frame. Received frames with CRC errors may optionally be dropped in the RX FIFO (refer to Section 5.1.1.3.6, “Filter CRC Error Packets” on page 68). Otherwise, the frames are sent to the SPI3 interface and may be dropped by the switch or system controller.

Frames transmitted by the MAC are also checked for correct CRC. When an incorrect CRC is detected on a transmitted frame, the TX CRCError RMON statistic counter is incremented for each incorrect frame.

5.1.2Flow Control

Flow Control is an IEEE 802.3x-defined mechanism for one network node to request that its link partner take a temporary “Pause” in packet transmission. This allows the requesting network node to prevent FIFO overruns and dropped packets, by managing incoming traffic to fit its available memory. The temporary pause allows the device to process packets already received or in transit, thus freeing up the FIFO space allocated to those packets.

69

Datasheet

Document Number: 278757

Revision Number: 009

Revision Date: 27-Oct-2005

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Intel IXF1104 manual Flow Control, CRC Error Detection, CRC Errored Packets Drop Enable Behavior
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IXF1104 specifications

The Intel IXF1104 is a cutting-edge Network Interface Controller (NIC) designed to meet the needs of high-speed communication in modern networking environments. As the demand for bandwidth-intensive applications continues to grow, Intel's IXF1104 is engineered to deliver exceptional performance, reliability, and scalability, making it an ideal choice for data centers and enterprise networks.

One of the main features of the IXF1104 is its support for high-speed Ethernet connectivity, providing up to 100 Gbps throughput. This capability allows organizations to handle large amounts of data traffic efficiently, accommodating everything from cloud computing to big data analytics. The NIC utilizes advanced packet processing technology which ensures minimal latency, enhancing the overall user experience.

The IXF1104 is built on a robust architecture that integrates Intel's latest processing technologies. It incorporates a multi-core processing engine that allows for parallel processing of network packets, improving the handling of simultaneous network requests. This architecture also supports offloading features, freeing up CPU resources for other critical tasks, which optimizes system performance.

In terms of technologies, the IXF1104 supports a variety of standards including Ethernet and Fiber Channel, making it versatile across different networking environments. Its compatibility with industry-standard networking protocols ensures that it can easily integrate into existing frameworks, facilitating seamless upgrades and expansions.

Another significant characteristic of the IXF1104 is its energy efficiency. With Intel’s focus on sustainability, this NIC is designed to consume less power relative to its performance output, thereby reducing overall operational costs for organizations. It employs dynamic power management features that adjust power usage based on demand, which is especially beneficial in large-scale deployments.

Additionally, security features are woven into the IXF1104 design, protecting sensitive data from potential threats. Hardware-based security functions, including encryption capabilities and secure boot processes, ensure that the NIC can safeguard data integrity against unauthorized access.

Overall, the Intel IXF1104 stands out in the crowded NIC market by offering high-performance capabilities, energy efficiency, and robust security features. Its combination of advanced technologies and characteristics positions it as a strategic asset for modern networks, empowering organizations to achieve their connectivity and performance goals in an increasingly data-driven world.
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