Intel IXF1104 manual RX Fifo Port Reset $0x59E, RX Fifo Errored Frame Drop Enable $0x59F Sheet 1

Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 122. RX FIFO Port Reset ($0x59E)

Bit	Name	Description		Type1	Default
Register Description: The soft reset register for each port in the RX block. Port ID = bit
position in the register. To make the reset active, the bit must be set High. For example, reset					0x00000000
of port 1 implies register value = 0000_0018. Setting the bit to 0 de-asserts the reset.
31:4	Reserved	Reserved		RO	0x0000000
	Reset RX FIFO for	Port 3
3		0 =	De-assert reset	R/W	0
	Port 3
		1 =	Reset
	Reset RX FIFO for	Port 2
2		0 =	De-assert reset	R/W	0
	Port 2
		1 =	Reset
	Reset RX FIFO for	Port 1
1		0 =	De-assert reset	R/W	0
	Port 1
		1 =	Reset
	Reset RX FIFO for	Port 0
0		0 =	De-assert reset	R/W	0
	Port 0
		1 =	Reset

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

Table 123. RX FIFO Errored Frame Drop Enable ($0x59F) (Sheet 1 of 2)

Bit	Name	Description	Type1	Default
Register Description: This register configures the dropping of error packets (DEBAD).
				0x00000000
NOTE: Jumbo packets are not dropped.
31:4	Reserved	Reserved	RO	0x0000000
		This bit is used in conjunction with MAC filter bits.
	RX FIFO Errored	This allows the user to select whether the errored
3	Frame Drop Enable	packets are to be dropped or not.	R/W	0
	Port 3	1 = Frame Drop Enable
		0 = Frame Drop Disable

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

Datasheet 196

Document Number: 278757

Revision Number: 009

Revision Date: 27-Oct-2005