Intel IXF1104 manual TX Fifo Errored Frame Drop Counter Ports 0 3 $0x625

Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 139. TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629)

Name	Description	Address	Type*	Default
	This register provides the number of packets
	dropped by the TX FIFO due to the following:
	Data Parity Errors
TX FIFO errored	Short SOPs (two consecutive SOPs for a port
	with no EOP)
frame drop counter		0x625	R	0x00000000
	Small Packets (9-14 bytes)
on Port 0
	Frames received that are signaled with TERR
	on the SPI3 TX interface.
	NOTE: This register is cleared on Read.
	This register provides the number of packets
	dropped by the TX FIFO due to the following:
	Data Parity Errors
TX FIFO errored	Short SOPs (two consecutive SOPs for a port
	with no EOP)
frame drop counter		0x626	R	0x00000000
	Small Packets (9-14 bytes)
on Port 1
	Frames received that are signaled with TERR
	on the SPI3 TX interface.
	NOTE: This register is cleared on Read.
	This register provides the number of packets
	dropped by the TX FIFO due to the following:
	Data Parity Errors
TX FIFO errored	Short SOPs (two consecutive SOPs for a port
	with no EOP)
frame drop counter		0x627	R	0x00000000
	Small Packets (9-14 bytes)
on Port 2
	Frames received that are signaled with TERR
	on the SPI3 TX interface.
	NOTE: This register is cleared on Read.
	This register provides the number of packets
	dropped by the TX FIFO due to the following:
	Data Parity Errors
TX FIFO errored	Short SOPs (two consecutive SOPs for a port
	with no EOP)
frame drop counter		0x628	R	0x00000000
	Small Packets (9-14 bytes)
on Port 3
	Frames received that are signaled with TERR
	on the SPI3 TX interface.
	NOTE: This register is cleared on Read.

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

209 Datasheet

Document Number: 278757

Revision Number: 009

Revision Date: 27-Oct-2005