Motorola MC9S12GC-Family, MC9S12C-Family warranty XFC Pin, Figure B-3 Basic PLL functional diagram

Device User Guide — 9S12C128DGV1/D V01.05

Cp

fosc

1

refdv+1

VDDPLL

	Cs	R	XFC Pin
fref	Δ	Phase		VCO
		KΦ		KV

fvco

fcmp

Detector

Loop Divider

11

synr+12

Figure B-3 Basic PLL functional diagram

The following procedure can be used to calculate the resistance and capacitance values using typical values for K1, f1 and ich from Table B-12.

The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used for fOSC = 4MHz and a 25MHz bus clock.

The VCO Gain at the desired VCO frequency is approximated by:

(f1	–fvco )
-----------------------
K1 ⋅ 1V		⋅ e
KV = K1 ⋅ e	= –100

The phase detector relationship is given by:

KΦ = –ich⋅ KV

ich is the current in tracking mode.

(60 –50)

-----------------------

–100= -90.48MHz/V

=316.7Hz/Ω

The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10, typical values are 50. ζ = 0.9 ensures a good transient response.

fC

2 ⋅ ζ ⋅ fref

1

→ fC

fref

;(ζ = 0.9)

< ------------------------------------------

------

<

4-------------

⋅ 10

⎛

2⎞

10

π ⋅ ⎝

ζ +

1 +

ζ

⎠

fC < 25kHz

112