Motorola MC9S12GC-Family, MC9S12C-Family warranty Table B-4 ATD Operating Characteristics

Device User Guide — 9S12C128DGV1/D V01.05

beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped

Table B-4 ATD Operating Characteristics

Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= VDDA <= 3.3V+10%

Num	C	Rating	Symbol	Min	Typ	Max	Unit
		Reference Potential	VRL	VSSA		VDDA/2	V
1	D	Low
		High	VRH	VDDA/2		VDDA	V
2	C	Differential Reference Voltage	VRH-VRL	3.0	3.3	3.6	V
3	D	ATD Clock Frequency	fATDCLK	0.5		2.0	MHz
		ATD 10-Bit Conversion Period
4	D	Clock Cycles1	NCONV10	14		28	Cycles
		Conv, Time at 2.0MHz ATD Clock fATDCLK	T	7		14	μs
			CONV10
		ATD 8-Bit Conversion Period
5	D	Clock Cycles(1)	NCONV8	12		26	Cycles
		Conv, Time at 2.0MHz ATD Clock fATDCLK	TCONV8	6		13	μs
6	D	Recovery Time (VDDA=3.3 Volts)	tREC			20	μs
7	P	Reference Supply current	IREF			0.250	mA
NOTES:

1.The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks.

B.4.3 Factors influencing accuracy

Three factors - source resistance, source capacitance and current injection - have an influenceon the accuracy of the ATD.

B.4.3.1 Source Resistance:

Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowable.

B.4.3.2 Source capacitance

When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage ≤ 1LSB, then the external filter capacitor, Cf ≥ 1024 * (CINS- CINN).

100