Motorola MC9S12C-Family Appendix C Electrical Specifications, Master Mode, Description Value Unit

Device User Guide — 9S12C128DGV1/D V01.05

B.8 SPI

Appendix C Electrical Specifications

This section provides electrical parametrics and ratings for the SPI.

In Table C-1the measurement conditions are listed.

Table C-1 Measurement Conditions

Description	Value	Unit
Drive mode	full drive mode	—
Load capacitance CLOAD,	50	pF
on all outputs
Thresholds for delay	(20% / 80%) VDDX	V
measurement points

C.1 Master Mode

In Figure C-1the timing diagram for master mode with transmission format CPHA=0 is depicted.

SS1
(OUTPUT)
2	1	12
SCK		4
(CPOL = 0)
(OUTPUT)	4
SCK		12
(CPOL = 1)
(OUTPUT)
5	6
MISO	MSB IN2	BIT 6 . . . 1
(INPUT)
10		9

MOSI	MSB OUT2	BIT 6 . . . 1
(OUTPUT)

1.if configured as an output.

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

13	3
13
LSB IN
	11
LSB OUT

Figure C-1 SPI Master Timing (CPHA=0)

In Figure C-2the timing diagram for master mode with transmission format CPHA=1 is depicted.

119