Motorola MC9S12C-Family warranty ATD Characteristics, ATD Operating Characteristics In 5V Range

Device User Guide — 9S12C128DGV1/D V01.05

B.4 ATD Characteristics

This section describes the characteristics of the analog to digital converter.

VRL is not available as a separate pin in the 48 and 52 pin versions. In this case the internal VRL pad is bonded to the VSSA pin.

The ATD is specified and tested for both the 3.3V and 5V range. For ranges between 3.3V and 5V the ATD accuracy is generally the same as in the 3.3V range but is not tested in this range in production test.

B.4.1 ATD Operating Characteristics In 5V Range

The Table B-3 shows conditions under which the ATD operates.

The following constraints exist to obtain full-scale, full range results:

VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped.

Table B-3 ATD Operating Characteristics

Conditions are shown in Table A-4 unless otherwise noted. Supply Voltage 5V-10% <= VDDA <=5V+10%

Num	C	Rating	Symbol	Min	Typ	Max	Unit
		Reference Potential	VRL	VSSA		VDDA/2	V
1	D	Low
		High	VRH	VDDA/2		VDDA	V
2	C	Differential Reference Voltage1	VRH-VRL	4.75	5.0	5.25	V
3	D	ATD Clock Frequency	fATDCLK	0.5		2.0	MHz
		ATD 10-Bit Conversion Period
4	D	Clock Cycles2	NCONV10	14		28	Cycles
		Conv, Time at 2.0MHz ATD Clock fATDCLK	TCONV10	7		14	μs
		ATD 8-Bit Conversion Period
5	D	Clock Cycles2	NCONV10	12		26	Cycles
		Conv, Time at 2.0MHz ATD Clock fATDCLK	TCONV10	6		13	μs
5	D	Recovery Time (VDDA=5.0 Volts)	tREC			20	μs
6	P	Reference Supply current	IREF			0.375	mA
NOTES:

1.Full accuracy is not guaranteed when differential voltage is less than 4.75V

2.The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks.

B.4.2 ATD Operating Characteristics In 3.3V Range

The Table B-3 shows conditions under which the ATD operates.

The following constraints exist to obtain full-scale, full range results:

VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive

99