Motorola MC9S12GC-Family, MC9S12C-Family instruction

Device User Guide — 9S12C128DGV1/D V01.05

Internal Pull

Pin Name

Pin Name

Pin Name

Power

Resistor

Description

Function 1

Function 2

Function 3

Domain

CTRL

Reset

State

PP[2:0]

KWP[2:0]

PW[2:0]

VDDX

PERP/

Disabled

Port P I/O Pins, keypad wake-up, PWM outputs

PPSP

PJ[7:6]

KWJ[7:6]

—

VDDX

PERJ/

Disabled

Port J I/O Pins and keypad wake-up

PPSJ

PM5

SCK

—

VDDX

PERM/

Up

Port M I/O Pin and SPI SCK signal

PPSM

PM4

MOSI

—

VDDX

PERM/

Up

Port M I/O Pin and SPI MOSI signal

PPSM

PERM/

PM3

SS

—

VDDX

Up

Port M I/O Pin and SPI SS signal

PPSM

PM2

MISO

—

VDDX

PERM/

Up

Port M I/O Pin and SPI MISO signal

PPSM

PM1

TXCAN

—

VDDX

PERM/

Up

Port M I/O Pin and CAN transmit signal2

PPSM

PM0

RXCAN

—

VDDX

PERM/

Up

Port M I/O Pin and CAN receive signal2

PPSM

PS[3:2]

—

—

VDDX

PERS/

Up

Port S I/O Pins

PPSS

PS1

TXD

—

VDDX

PERS/

Up

Port S I/O Pin and SCI transmit signal

PPSS

PS0

RXD

—

VDDX

PERS/

Up

Port S I/O Pin and SCI receive signal

PPSS

PT[7:5]

IOC[7:5]

—

VDDX

PERT/

Disabled

Port T I/O Pins shared with timer (TIM)

PPST

PT[4:0]

IOC[4:0]

PW[4:0]

VDDX

PERT/

Disabled

Port T I/O Pins shared with timer and PWM

PPST

NOTES:

1.The PortE output buffer enable signal control at reset is determined by the PEAR register and is mode dependent. E.g. in special test mode RDWE=LSTRE=1 which enables the PE[3:2] output buffers and disables the pull-ups. Refer to S12_MEBI user guide for PEAR register details.

2.CAN functionality is not available on the MC9S12GC-Family members

2.2.1 Pin Initialization for 48 & 52 Pin LQFP bond-out versions

Not Bonded Pins If the port pins are not bonded out in the chosen package the user should initialize the registers to be inputs with enabled pull resistance to avoid excess current consumption. This applies to the following pins:

(48LQFP): Port A[7:1], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[4:0], Port J[7:6], PortS[3:2]

(52LQFP): Port A[7:3], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[2:0], Port J[7:6], PortS[3:2]

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Image 56

Motorola MC9S12GC-Family, MC9S12C-Family warranty Pin Initialization for 48 & 52 Pin Lqfp bond-out versions

Contents

Document Number 9S12C128DGV1/D Revision History Device User Guide 9S12C128DGV1/D Table of Contents Resets and Interrupts System Clock Description Modes of Operation HCS12 Core Block Description Voltage Regulator Vreg Block Description Appendix B Electrical Specifications Appendix E Emulation Information Appendix C Electrical SpecificationsAppendix D Package Information Device User Guide 9S12C128DGV1/D List of Figures Device User Guide 9S12C128DGV1/D List of Tables Device User Guide 9S12C128DGV1/D Device User Guide 9S12C128DGV1/D Device User Guide 9S12C128DGV1/D Preface List of MC9S12C and MC9S12GC Family membersMC9S12C-Family Package Option Summary Package Device Part Number Mask Temp Flash TBD 48LQFP Speed Options 25 = 25MHz bus 16 = 16MHz busPart Number Mask Temp Package Speed Description Set MC9S12C96PCFA16 MC9S12C96PCPB16MC9S12C96PCFU16 MC9S12C96PVFA16 MC9S12C96PMFA25 MC9S12C96PMPB25MC9S12C96PMFU25 MC9S12C64PCFA16 MC9S12GC-Family Part Number Coding MC9S12GC64CFA25 TBD MC9S12GC64CPB25 TBDMC9S12GC64CFU25 TBD MC9S12GC64PVFA25 User Guide Version Document Order Number TerminologyDocument References Device User Guide 9S12C128DGV1/D Overview FeaturesIntroduction Device User Guide 9S12C128DGV1/D Modes of Operation Special Test ModeMotorola use only Block Diagram MC9S12C-Family Block Diagram Address Module Size Device Memory MapDevice Register Map Overview MC9S12C128 and MC9S12GC128 User configurable Memory Map MC9S12C96 User Configurable Memory Map MC9S12C64 and MC9S12GC64 User Configurable Memory Map MC9S12C32 and MC9S12GC32 User Configurable Memory Map MC9S12GC16 User Configurable Memory Map Detailed Register Map $0010 $0014 MMC map 1 of 4 HCS12 Module Mapping Control Ivis $0015 $0016 INT map 1 of 2 HCS12 Interrupt $0017 $0017 MMC map 2 of 4 HCS12 Module Mapping Control$0018 $0018 Miscellaneous Peripherals Device User Guide $001F $001F INT map 2 of 2 HCS12 Interrupt $0020 $002F DBG including BKP map 1 of 1 HCS12 Debug $0034 $003F CRG Clock and Reset Generator $0030 $0031 MMC map 4 of 4 HCS12 Module Mapping Control $0040 $006F TIM Timer 16 Bit 8 Channels $0050 $0070 $007F $00A0 $00C7 Reserved $00C8 $00CF SCI Asynchronous Serial Interface $00D0 $00D7Reserved $00D8 $00DF SPI Serial Peripheral Interface TIE $00E0 $00FF PWM Pulse Width Modulator $0100 $010F Flash Control Register Time $0110 $013F$0140 $017F Reserved Can Motorola Scalable can MSCAN1 $0140 $017F Can Motorola Scalable can MSCAN1 $0180 $023F Reserved $0240 $027F PIM Port Interface ModulePRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 Ptis PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 PTIAD7 PTIAD6 PTIAD5 PTIAD4 PTIAD3 PTIAD2 PTIAD1 PTIJ7DDRAD7 DDRAD2 Part ID Assignments $0280 $03FF Reserved spaceAssigned Part ID Numbers Memory size registers MC9S12C32, MC9S12GC32 Signal Description Device Pinout PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 PW4/IOC4/PT4 Pin Assignments in 48 Lqfp for MC9S12C-Family Signal Properties Summary Signal PropertiesInternal Pull Resistor Description Function Domain Pin Initialization for 48 & 52 Pin Lqfp bond-out versions Device User Guide 9S12C128DGV1/D Internal Pull Pin Name Detailed Signal Descriptions EXTAL, Xtal Oscillator PinsReset External Reset Pin Test / VPP Test Pin Bkgd / Taghi / Modc Background Debug, Tag High & Mode Pin 6 PA70 / ADDR158 / DATA158 Port a I/O Pins7 PB70 / ADDR70 / DATA70 Port B I/O Pins 8 PE7 / Noacc / Xclks Port E I/O Pin Colpitts Oscillator Connections PE7=1 Pierce Oscillator Connections PE7=0 9 PE6 / Modb / IPIPE1 Port E I/O Pin 10 PE5 / Moda / IPIPE0 Port E I/O Pin11 PE4 / ECLK- Port E I/O Pin 4 / E-Clock Output 12 PE3 / Lstrb Port E I/O Pin 3 / Low-Byte Strobe Lstrb 16 PAD70 / AN70 Port AD I/O Pins 14 PE1 / IRQ Port E input Pin 1 / Maskable Interrupt Pin17 PP7 / KWP7 Port P I/O Pin 18 PP6 / KWP6/ROMCTL Port P I/O Pin 19 PP50 / KWP50 / PW50 Port P I/O Pins 20 PJ76 / KWJ76 Port J I/O Pins21 PM5 / SCK Port M I/O Pin 22 PM4 / Mosi Port M I/O Pin Power Supply Pins VDDA, Vssa Power Supply Pins for ATD and Vreg 5 VRH, VRL ATD Reference Voltage Input PinsVDDPLL, Vsspll Power Supply Pins for PLL MC9S12C-Family Power and Ground Connection Summary Chip Configuration Summary Modes of Operation Clock Selection Based on PE7 Mode SelectionSecurity Low Power Modes Securing the MicrocontrollerOperation of the Secured Microcontroller Unsecuring the Microcontroller Resets and Interrupts Vectors Resets Reset Summary Table Effects of ResetHCS12 Core Block Description Device-specific information Device Visible with Ppage contents BDM alternate clockExtended Address Range Emulation Implications Device Specific Flash page Mapping Voltage Regulator Vreg Block Description Recommended Printed Circuit Board LayoutVregen 2 VDD1, VDD2, VSS1, VSS2 Recommended External Component Values Component Purpose Type Value Recommended PCB Layout 48 Lqfp Recommended PCB Layout 52 Lqfp Recommended PCB Layout 80 QFP VSS2 Recommended PCB Layout for 48 Lqfp Pierce Oscillator Recommended PCB Layout for 52 Lqfp Pierce Oscillator Clock Reset Generator CRG Block Description Recommended PCB Layout for 80QFP Pierce Oscillator Timer TIM Block Description Oscillator OSC Block DescriptionAnalog to Digital Converter ATD Block Description Serial Communications Interface SCI Block Description Flash Block Description RAM Block DescriptionPulse Width Modulator PWM Block Description Mscan Block Description Device User Guide 9S12C128DGV1/D Appendix a Electrical Characteristics Power SupplyGeneral Parameter Classification Pins Current Injection Table A-1 Absolute Maximum Ratings Num Rating Symbol Min Max UnitAbsolute Maximum Ratings Table A-3 ESD and Latch-Up Protection Characteristics Model Description Symbol Value UnitESD Protection and Latch-up Immunity Operating Conditions Table A-4 Operating Conditions Power Dissipation and Thermal CharacteristicsRating Symbol Min Typ Max Unit Pint = IDD ⋅ VDD + Iddpll ⋅ Vddpll + Idda ⋅ Vdda Num Rating Symbol Min Typ Max Unit 9 I/O CharacteristicsTable A-5 Thermal Package Characteristics1 Table A-6 5V I/O Characteristics Table A-7 3.3V I/O Characteristics Num Rating Symbol Min Typ Additional Remarks Supply CurrentsMeasurement Conditions Table A-8 Supply Current Characteristics for MC9S12C32 Stop Current 40 C 27 C Appendix B Electrical Specifications Characteristic Symbol Min Typical Max UnitVoltage Regulator Operating Conditions Table B-1 Voltage Regulator Electrical Parameters Chip Power-up and LVI/LVR graphical explanation Output LoadsResistive Loads LVI Table B-2 Voltage Regulator Capacitive Loads Num Characteristic Symbol Min Typical Max UnitCapacitive Loads Device User Guide 9S12C128DGV1/D ATD Characteristics ATD Operating Characteristics In 5V RangeATD Operating Characteristics In 3.3V Range Table B-3 ATD Operating Characteristics Table B-4 ATD Operating Characteristics Factors influencing accuracySource Resistance Source capacitance Table B-5 ATD Electrical Characteristics Current injection ATD accuracy 5V Range ATD accuracy 3.3V RangeTable B-6 ATD Conversion Performance Table B-7 ATD Conversion Performance 1LSB Figure B-2 ATD Accuracy Definitions NVM, Flash and Eeprom NVM timingSingle Word Programming Row Programming Mass Erase Table B-8 NVM Timing CharacteristicsSector Erase Table B-9 NVM Reliability Characteristics NVM Reliability 108 Reset, Oscillator and PLL Startup External Reset Stop RecoveryPseudo Stop and Wait Recovery Oscillator XFC Component Selection Phase Locked LoopTable B-11 Oscillator Characteristics Figure B-3 Basic PLL functional diagram XFC Pin ⋅ synr + Jitter Information = max ⎜ ⋅ t nom Table B-12 PLL Characteristics 116 Table B-13 Mscan Wake-up Pulse Characteristics Num Rating Symbol Min Typ Max 118 Appendix C Electrical Specifications Master ModeTable C-1 Measurement Conditions Description Value Unit Table C-2 SPI Master Mode Timing Characteristics Num Characteristic Symbol Unit Min Typ MaxMosi Port Data LSB Master LSB OUT Slave Mode Input SCKInput Miso Slave MSB Table C-3 SPI Slave Mode Timing Characteristics Num Characteristic Symbol Unit Min TypMosi Input Slave MSB OUT Slave LSB OUT External Bus Timing General Muxed Bus TimingEclk PE4 PE2 Lstrb PE3 Noacc PE7 PIPO0 PIPO1, PE6,5 Table C-4 Expanded Bus Timing Characteristics 5V Range Pweh Table C-5 Expanded Bus Timing Characteristics 3.3V Range 126 Appendix D Package Information Figure D-1 80-pin QFP Mechanical Dimensions case no B 80-pin QFP package Figure D-2 52-pin Lqfp Mechanical Dimensions case no D-03 52-pin Lqfp package 48-pin Lqfp package Section AE-AE Detail AD Appendix E Emulation Information 1 PK20 / XADDR1614 112-pin Lqfp package 134 Device User Guide End Sheet 136