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Motorola MC9S12GC-Family, MC9S12C-Family warranty 1 PK20 / XADDR1614

Models: MC9S12C-Family MC9S12GC-Family

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Device User Guide — 9S12C128DGV1/D V01.05

E.1.1 PK[2:0] / XADDR[16:14]

PK2-PK0 provide the expanded address XADDR[16:14] for the external bus.

Refer to the S12 Core user guide for detailed information about external address page access.

				Internal Pull
	Pin Name	Pin Name	Power	Resistor		Description
	Function 1	Function 2	Domain	CTRL	Reset	Description
	Function 1	Function 2	Domain		Reset
					State
					State

	PK[2:0]	XADDR[16:14]	VDDX	PUPKE	Up	Port K I/O Pins

The reset state of DDRK in the S12_CORE is $00, configuring the pins as inputs.

The reset state of PUPKE in the PUCR register of the S12_CORE is "1" enabling the internal pullup resistors at PortK[2:0].

In this reset state the pull-up resistors provide a defined state and prevent a floating input, thereby preventing unneccesary current consumption at the input stage.

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Motorola MC9S12GC-Family, MC9S12C-Family warranty 1 PK20 / XADDR1614

Contents

Document Number 9S12C128DGV1/D Revision History Device User Guide 9S12C128DGV1/DTable of Contents Resets and Interrupts System Clock Description Modes of OperationHCS12 Core Block Description Voltage Regulator Vreg Block DescriptionAppendix B Electrical Specifications Appendix C Electrical Specifications Appendix D Package InformationAppendix E Emulation Information Device User Guide 9S12C128DGV1/D List of Figures Device User Guide 9S12C128DGV1/D List of Tables Device User Guide 9S12C128DGV1/D Device User Guide 9S12C128DGV1/D Device User Guide 9S12C128DGV1/D Preface List of MC9S12C and MC9S12GC Family membersMC9S12C-Family Package Option Summary Package Device Part Number Mask Temp FlashSpeed Options 25 = 25MHz bus 16 = 16MHz bus Part Number Mask Temp Package Speed Description SetTBD 48LQFP MC9S12C96PCFA16 MC9S12C96PCPB16MC9S12C96PCFU16 MC9S12C96PVFA16MC9S12C96PMFA25 MC9S12C96PMPB25MC9S12C96PMFU25 MC9S12C64PCFA16MC9S12GC-Family Part Number Coding MC9S12GC64CFA25 TBD MC9S12GC64CPB25 TBDMC9S12GC64CFU25 TBD MC9S12GC64PVFA25Terminology Document ReferencesUser Guide Version Document Order Number Device User Guide 9S12C128DGV1/D Features IntroductionOverview Device User Guide 9S12C128DGV1/D Modes of Operation Special Test ModeMotorola use only Block Diagram MC9S12C-Family Block DiagramDevice Memory Map Device Register Map OverviewAddress Module Size MC9S12C128 and MC9S12GC128 User configurable Memory Map MC9S12C96 User Configurable Memory Map MC9S12C64 and MC9S12GC64 User Configurable Memory Map MC9S12C32 and MC9S12GC32 User Configurable Memory Map MC9S12GC16 User Configurable Memory Map Detailed Register Map$0010 $0014 MMC map 1 of 4 HCS12 Module Mapping Control Ivis$0015 $0016 INT map 1 of 2 HCS12 Interrupt $0017 $0017 MMC map 2 of 4 HCS12 Module Mapping Control$0018 $0018 Miscellaneous Peripherals Device User Guide$001F $001F INT map 2 of 2 HCS12 Interrupt $0020 $002F DBG including BKP map 1 of 1 HCS12 Debug$0034 $003F CRG Clock and Reset Generator $0030 $0031 MMC map 4 of 4 HCS12 Module Mapping Control$0040 $006F TIM Timer 16 Bit 8 Channels $0050 $0070 $007F $00A0 $00C7 Reserved$00C8 $00CF SCI Asynchronous Serial Interface $00D0 $00D7Reserved $00D8 $00DF SPI Serial Peripheral Interface TIE$00E0 $00FF PWM Pulse Width Modulator $0100 $010F Flash Control Register $0110 $013F $0140 $017F Reserved Can Motorola Scalable can MSCAN1Time $0140 $017F Can Motorola Scalable can MSCAN1 $0180 $023F Reserved $0240 $027F PIM Port Interface ModulePRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0Ptis PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 PTIAD7 PTIAD6 PTIAD5 PTIAD4 PTIAD3 PTIAD2 PTIAD1 PTIJ7DDRAD7 DDRAD2Part ID Assignments $0280 $03FF Reserved spaceAssigned Part ID Numbers Memory size registersMC9S12C32, MC9S12GC32 Signal Description Device PinoutPW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 PW4/IOC4/PT4Pin Assignments in 48 Lqfp for MC9S12C-Family Signal Properties Summary Signal PropertiesInternal Pull Resistor Description Function DomainPin Initialization for 48 & 52 Pin Lqfp bond-out versions Device User Guide 9S12C128DGV1/D Internal Pull Pin NameDetailed Signal Descriptions EXTAL, Xtal Oscillator PinsReset External Reset Pin Test / VPP Test PinBkgd / Taghi / Modc Background Debug, Tag High & Mode Pin 6 PA70 / ADDR158 / DATA158 Port a I/O Pins7 PB70 / ADDR70 / DATA70 Port B I/O Pins 8 PE7 / Noacc / Xclks Port E I/O PinColpitts Oscillator Connections PE7=1 Pierce Oscillator Connections PE7=09 PE6 / Modb / IPIPE1 Port E I/O Pin 10 PE5 / Moda / IPIPE0 Port E I/O Pin11 PE4 / ECLK- Port E I/O Pin 4 / E-Clock Output 12 PE3 / Lstrb Port E I/O Pin 3 / Low-Byte Strobe Lstrb16 PAD70 / AN70 Port AD I/O Pins 14 PE1 / IRQ Port E input Pin 1 / Maskable Interrupt Pin17 PP7 / KWP7 Port P I/O Pin 18 PP6 / KWP6/ROMCTL Port P I/O Pin19 PP50 / KWP50 / PW50 Port P I/O Pins 20 PJ76 / KWJ76 Port J I/O Pins21 PM5 / SCK Port M I/O Pin 22 PM4 / Mosi Port M I/O PinPower Supply Pins VDDA, Vssa Power Supply Pins for ATD and Vreg 5 VRH, VRL ATD Reference Voltage Input PinsVDDPLL, Vsspll Power Supply Pins for PLL MC9S12C-Family Power and Ground Connection SummaryChip Configuration Summary Modes of OperationMode Selection SecurityClock Selection Based on PE7 Low Power Modes Securing the MicrocontrollerOperation of the Secured Microcontroller Unsecuring the MicrocontrollerResets and Interrupts VectorsResets Reset Summary Table Effects of ResetHCS12 Core Block Description Device-specific informationDevice Visible with Ppage contents BDM alternate clockExtended Address Range Emulation Implications Device Specific Flash page MappingVoltage Regulator Vreg Block Description Recommended Printed Circuit Board LayoutVregen 2 VDD1, VDD2, VSS1, VSS2Recommended External Component Values Component Purpose Type ValueRecommended PCB Layout 48 Lqfp Recommended PCB Layout 52 Lqfp Recommended PCB Layout 80 QFP VSS2Recommended PCB Layout for 48 Lqfp Pierce Oscillator Recommended PCB Layout for 52 Lqfp Pierce Oscillator Clock Reset Generator CRG Block Description Recommended PCB Layout for 80QFP Pierce OscillatorTimer TIM Block Description Oscillator OSC Block DescriptionAnalog to Digital Converter ATD Block Description Serial Communications Interface SCI Block DescriptionFlash Block Description RAM Block DescriptionPulse Width Modulator PWM Block Description Mscan Block DescriptionDevice User Guide 9S12C128DGV1/D Appendix a Electrical Characteristics Power SupplyGeneral Parameter ClassificationPins Current InjectionNum Rating Symbol Min Max Unit Absolute Maximum RatingsTable A-1 Absolute Maximum Ratings Table A-3 ESD and Latch-Up Protection Characteristics Model Description Symbol Value UnitESD Protection and Latch-up Immunity Operating ConditionsPower Dissipation and Thermal Characteristics Rating Symbol Min Typ Max UnitTable A-4 Operating Conditions Pint = IDD ⋅ VDD + Iddpll ⋅ Vddpll + Idda ⋅ Vdda 9 I/O Characteristics Table A-5 Thermal Package Characteristics1Num Rating Symbol Min Typ Max Unit Table A-6 5V I/O Characteristics Table A-7 3.3V I/O Characteristics Num Rating Symbol Min TypSupply Currents Measurement ConditionsAdditional Remarks Table A-8 Supply Current Characteristics for MC9S12C32 Stop Current 40 C 27 C Appendix B Electrical Specifications Characteristic Symbol Min Typical Max UnitVoltage Regulator Operating Conditions Table B-1 Voltage Regulator Electrical ParametersChip Power-up and LVI/LVR graphical explanation Output LoadsResistive Loads LVINum Characteristic Symbol Min Typical Max Unit Capacitive LoadsTable B-2 Voltage Regulator Capacitive Loads Device User Guide 9S12C128DGV1/D ATD Characteristics ATD Operating Characteristics In 5V RangeATD Operating Characteristics In 3.3V Range Table B-3 ATD Operating CharacteristicsTable B-4 ATD Operating Characteristics Factors influencing accuracySource Resistance Source capacitanceTable B-5 ATD Electrical Characteristics Current injectionATD accuracy 5V Range ATD accuracy 3.3V RangeTable B-6 ATD Conversion Performance Table B-7 ATD Conversion Performance1LSB Figure B-2 ATD Accuracy Definitions NVM, Flash and Eeprom NVM timingSingle Word Programming Row ProgrammingTable B-8 NVM Timing Characteristics Sector EraseMass Erase Table B-9 NVM Reliability Characteristics NVM Reliability108 Reset, Oscillator and PLL StartupExternal Reset Stop RecoveryPseudo Stop and Wait Recovery OscillatorPhase Locked Loop Table B-11 Oscillator CharacteristicsXFC Component Selection Figure B-3 Basic PLL functional diagram XFC Pin⋅ synr + Jitter Information= max ⎜ ⋅ t nom Table B-12 PLL Characteristics 116 Table B-13 Mscan Wake-up Pulse Characteristics Num Rating Symbol Min Typ Max118 Appendix C Electrical Specifications Master ModeTable C-1 Measurement Conditions Description Value UnitTable C-2 SPI Master Mode Timing Characteristics Num Characteristic Symbol Unit Min Typ MaxMosi Port Data LSB Master LSB OUTSlave Mode Input SCKInput Miso Slave MSBTable C-3 SPI Slave Mode Timing Characteristics Num Characteristic Symbol Unit Min TypMosi Input Slave MSB OUT Slave LSB OUTExternal Bus Timing General Muxed Bus TimingEclk PE4 PE2 Lstrb PE3 Noacc PE7 PIPO0 PIPO1, PE6,5Table C-4 Expanded Bus Timing Characteristics 5V Range PwehTable C-5 Expanded Bus Timing Characteristics 3.3V Range 126 Appendix D Package Information Figure D-1 80-pin QFP Mechanical Dimensions case no B 80-pin QFP packageFigure D-2 52-pin Lqfp Mechanical Dimensions case no D-03 52-pin Lqfp package48-pin Lqfp package Section AE-AE Detail ADAppendix E Emulation Information 1 PK20 / XADDR1614 112-pin Lqfp package 134 Device User Guide End Sheet 136