Revision History | Motorola MC9S12GC-Family, MC9S12C-Family specification

Device User Guide — 9S12C128DGV1/D V01.05

Revision History

	Version	Revision	Effective	Author	Description of Changes
	Number	Date	Date	Author	Description of Changes
	Number	Date	Date

	00.01	25.JAN.03	25.JAN.03		Original Version. Based on C32 user guide version 01.12

	00.02	07.FEB.03	07.FEB.03		Enhanced PortK description
	00.02	07.FEB.03	07.FEB.03		Part number table revision in preface
					Part number table revision in preface

					QFP112 Emulation pinout correction
	00.03	25.FEB.03	25.FEB.03		Enhanced part number explanation in preface
					Reduced pseudo STOP current spec. for C64,C96,C128

					Enhanced PortAD signal description
	00.04	15.APR.03	15.APR03		Corrected VDDR description in 2.4.2
					Revised pin leakage in electrical parameters

					SPI timing parameter table correction
					Output drive high value reduced in 3V range
	00.05	05.MAY.03	05.MAY.03		PE[4:2] Pull-Up spec out of reset changed
					3V Expansion bus timing parameters not tested in production
					Minimum bus frequency speciﬁcation increased to 0.25MHz.

	00.06	21.MAY.03	21.MAY.03		Parameter classiﬁcation added to Appendix Table C-2.
	00.06	21.MAY.03	21.MAY.03		IOH changed to 4mA for 3V range.
					IOH changed to 4mA for 3V range.

					LVR level deﬁned.for C32. Run IDD changed for C32.
	01.00	15.JUL.03	15.JUL03		Block guide reference table updated
	01.00	15.JUL.03	15.JUL03		Added PCB layout guide for Pierce oscillator conﬁguration
					Added PCB layout guide for Pierce oscillator conﬁguration
					IOL parameter updated in 3.3V range

	01.01	12.AUG.03	12.AUG.03		Updated PARTID listing due to C128 ECO revision

					Changed DOC number and CPU DOC reference number
	01.02	20.NOV.03	20.NOV.03		Included separate C32 LVI levels
					Changed PortM pull up reset state to enabled.

					Added References to the CAN-less GC-Family
					No major revision number increment, since silicon functionality is
	01.03	27.NOV.03	27.NOV.03		not changed.
					Added VDDX connection in PCB layout ﬁgures 8-1.to 8-6
					Added Part ID for 2L45J mask set to Part ID table

					Table A-4 VDD/VDDPLL min when supplied externally now 2.35V
	01.04	27.JAN.04	27.JAN.04		Reference S12FTS128K1 in Preface (was S12FTS128K)
					Reference to CPU Guide corrected to Version2

					Corrected ﬂash sector sizes for C-Family devices with >64K Flash
	01.05	11.FEB.04	11.FEB.04		Corrected Preface Table 0-1 16K part listing to GC16 without CAN
	01.05	11.FEB.04	11.FEB.04		Added PPAGE speciﬁcations to memory map diagrams
					Added PPAGE speciﬁcations to memory map diagrams
					Added ﬂash timing parameters for 1024 byte sector size

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Motorola MC9S12GC-Family, MC9S12C-Family warranty Revision History, Device User Guide 9S12C128DGV1/D

Contents

Document Number 9S12C128DGV1/D Revision History Device User Guide 9S12C128DGV1/D Table of Contents Resets and Interrupts System Clock Description Modes of Operation HCS12 Core Block Description Voltage Regulator Vreg Block Description Appendix B Electrical Specifications Appendix E Emulation Information Appendix C Electrical SpecificationsAppendix D Package Information Device User Guide 9S12C128DGV1/D List of Figures Device User Guide 9S12C128DGV1/D List of Tables Device User Guide 9S12C128DGV1/D Device User Guide 9S12C128DGV1/D Device User Guide 9S12C128DGV1/D MC9S12C-Family Package Option Summary PrefaceList of MC9S12C and MC9S12GC Family members Package Device Part Number Mask Temp Flash TBD 48LQFP Speed Options 25 = 25MHz bus 16 = 16MHz busPart Number Mask Temp Package Speed Description Set MC9S12C96PCFU16 MC9S12C96PCFA16MC9S12C96PCPB16 MC9S12C96PVFA16 MC9S12C96PMFU25 MC9S12C96PMFA25MC9S12C96PMPB25 MC9S12C64PCFA16 MC9S12GC-Family Part Number Coding MC9S12GC64CFU25 TBD MC9S12GC64CFA25 TBDMC9S12GC64CPB25 TBD MC9S12GC64PVFA25 User Guide Version Document Order Number TerminologyDocument References Device User Guide 9S12C128DGV1/D Overview FeaturesIntroduction Device User Guide 9S12C128DGV1/D Modes of Operation Special Test ModeMotorola use only Block Diagram MC9S12C-Family Block Diagram Address Module Size Device Memory MapDevice Register Map Overview MC9S12C128 and MC9S12GC128 User configurable Memory Map MC9S12C96 User Configurable Memory Map MC9S12C64 and MC9S12GC64 User Configurable Memory Map MC9S12C32 and MC9S12GC32 User Configurable Memory Map MC9S12GC16 User Configurable Memory Map Detailed Register Map $0010 $0014 MMC map 1 of 4 HCS12 Module Mapping Control Ivis $0018 $0018 $0015 $0016 INT map 1 of 2 HCS12 Interrupt$0017 $0017 MMC map 2 of 4 HCS12 Module Mapping Control Miscellaneous Peripherals Device User Guide $001F $001F INT map 2 of 2 HCS12 Interrupt $0020 $002F DBG including BKP map 1 of 1 HCS12 Debug $0034 $003F CRG Clock and Reset Generator $0030 $0031 MMC map 4 of 4 HCS12 Module Mapping Control $0040 $006F TIM Timer 16 Bit 8 Channels $0050 $0070 $007F $00A0 $00C7 Reserved Reserved $00D8 $00DF SPI Serial Peripheral Interface $00C8 $00CF SCI Asynchronous Serial Interface$00D0 $00D7 TIE $00E0 $00FF PWM Pulse Width Modulator $0100 $010F Flash Control Register Time $0110 $013F$0140 $017F Reserved Can Motorola Scalable can MSCAN1 $0140 $017F Can Motorola Scalable can MSCAN1 PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 $0180 $023FReserved $0240 $027F PIM Port Interface Module MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 Ptis DDRAD7 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0PTIAD7 PTIAD6 PTIAD5 PTIAD4 PTIAD3 PTIAD2 PTIAD1 PTIJ7 DDRAD2 Assigned Part ID Numbers Part ID Assignments$0280 $03FF Reserved space Memory size registers MC9S12C32, MC9S12GC32 Signal Description Device Pinout PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 PW4/IOC4/PT4 Pin Assignments in 48 Lqfp for MC9S12C-Family Internal Pull Signal Properties SummarySignal Properties Resistor Description Function Domain Pin Initialization for 48 & 52 Pin Lqfp bond-out versions Device User Guide 9S12C128DGV1/D Internal Pull Pin Name Reset External Reset Pin Detailed Signal DescriptionsEXTAL, Xtal Oscillator Pins Test / VPP Test Pin 7 PB70 / ADDR70 / DATA70 Port B I/O Pins Bkgd / Taghi / Modc Background Debug, Tag High & Mode Pin6 PA70 / ADDR158 / DATA158 Port a I/O Pins 8 PE7 / Noacc / Xclks Port E I/O Pin Colpitts Oscillator Connections PE7=1 Pierce Oscillator Connections PE7=0 11 PE4 / ECLK- Port E I/O Pin 4 / E-Clock Output 9 PE6 / Modb / IPIPE1 Port E I/O Pin10 PE5 / Moda / IPIPE0 Port E I/O Pin 12 PE3 / Lstrb Port E I/O Pin 3 / Low-Byte Strobe Lstrb 17 PP7 / KWP7 Port P I/O Pin 16 PAD70 / AN70 Port AD I/O Pins14 PE1 / IRQ Port E input Pin 1 / Maskable Interrupt Pin 18 PP6 / KWP6/ROMCTL Port P I/O Pin 21 PM5 / SCK Port M I/O Pin 19 PP50 / KWP50 / PW50 Port P I/O Pins20 PJ76 / KWJ76 Port J I/O Pins 22 PM4 / Mosi Port M I/O Pin Power Supply Pins VDDPLL, Vsspll Power Supply Pins for PLL VDDA, Vssa Power Supply Pins for ATD and Vreg5 VRH, VRL ATD Reference Voltage Input Pins MC9S12C-Family Power and Ground Connection Summary Chip Configuration Summary Modes of Operation Clock Selection Based on PE7 Mode SelectionSecurity Operation of the Secured Microcontroller Low Power ModesSecuring the Microcontroller Unsecuring the Microcontroller Resets and Interrupts Vectors Resets HCS12 Core Block Description Reset Summary TableEffects of Reset Device-specific information Extended Address Range Emulation Implications Device Visible with Ppage contentsBDM alternate clock Device Specific Flash page Mapping Vregen Voltage Regulator Vreg Block DescriptionRecommended Printed Circuit Board Layout 2 VDD1, VDD2, VSS1, VSS2 Recommended External Component Values Component Purpose Type Value Recommended PCB Layout 48 Lqfp Recommended PCB Layout 52 Lqfp Recommended PCB Layout 80 QFP VSS2 Recommended PCB Layout for 48 Lqfp Pierce Oscillator Recommended PCB Layout for 52 Lqfp Pierce Oscillator Clock Reset Generator CRG Block Description Recommended PCB Layout for 80QFP Pierce Oscillator Analog to Digital Converter ATD Block Description Timer TIM Block DescriptionOscillator OSC Block Description Serial Communications Interface SCI Block Description Pulse Width Modulator PWM Block Description Flash Block DescriptionRAM Block Description Mscan Block Description Device User Guide 9S12C128DGV1/D General Appendix a Electrical CharacteristicsPower Supply Parameter Classification Pins Current Injection Table A-1 Absolute Maximum Ratings Num Rating Symbol Min Max UnitAbsolute Maximum Ratings ESD Protection and Latch-up Immunity Table A-3 ESD and Latch-Up Protection CharacteristicsModel Description Symbol Value Unit Operating Conditions Table A-4 Operating Conditions Power Dissipation and Thermal CharacteristicsRating Symbol Min Typ Max Unit Pint = IDD ⋅ VDD + Iddpll ⋅ Vddpll + Idda ⋅ Vdda Num Rating Symbol Min Typ Max Unit 9 I/O CharacteristicsTable A-5 Thermal Package Characteristics1 Table A-6 5V I/O Characteristics Table A-7 3.3V I/O Characteristics Num Rating Symbol Min Typ Additional Remarks Supply CurrentsMeasurement Conditions Table A-8 Supply Current Characteristics for MC9S12C32 Stop Current 40 C 27 C Voltage Regulator Operating Conditions Appendix B Electrical SpecificationsCharacteristic Symbol Min Typical Max Unit Table B-1 Voltage Regulator Electrical Parameters Resistive Loads Chip Power-up and LVI/LVR graphical explanationOutput Loads LVI Table B-2 Voltage Regulator Capacitive Loads Num Characteristic Symbol Min Typical Max UnitCapacitive Loads Device User Guide 9S12C128DGV1/D ATD Operating Characteristics In 3.3V Range ATD CharacteristicsATD Operating Characteristics In 5V Range Table B-3 ATD Operating Characteristics Source Resistance Table B-4 ATD Operating CharacteristicsFactors influencing accuracy Source capacitance Table B-5 ATD Electrical Characteristics Current injection Table B-6 ATD Conversion Performance ATD accuracy 5V RangeATD accuracy 3.3V Range Table B-7 ATD Conversion Performance 1LSB Figure B-2 ATD Accuracy Definitions Single Word Programming NVM, Flash and EepromNVM timing Row Programming Mass Erase Table B-8 NVM Timing CharacteristicsSector Erase Table B-9 NVM Reliability Characteristics NVM Reliability 108 Reset, Oscillator and PLL Startup Pseudo Stop and Wait Recovery External ResetStop Recovery Oscillator XFC Component Selection Phase Locked LoopTable B-11 Oscillator Characteristics Figure B-3 Basic PLL functional diagram XFC Pin ⋅ synr + Jitter Information = max ⎜ ⋅ t nom Table B-12 PLL Characteristics 116 Table B-13 Mscan Wake-up Pulse Characteristics Num Rating Symbol Min Typ Max 118 Table C-1 Measurement Conditions Appendix C Electrical SpecificationsMaster Mode Description Value Unit Mosi Port Data Table C-2 SPI Master Mode Timing CharacteristicsNum Characteristic Symbol Unit Min Typ Max LSB Master LSB OUT Input Miso Slave ModeInput SCK Slave MSB Mosi Input Slave MSB OUT Table C-3 SPI Slave Mode Timing CharacteristicsNum Characteristic Symbol Unit Min Typ Slave LSB OUT Eclk PE4 External Bus TimingGeneral Muxed Bus Timing PE2 Lstrb PE3 Noacc PE7 PIPO0 PIPO1, PE6,5 Table C-4 Expanded Bus Timing Characteristics 5V Range Pweh Table C-5 Expanded Bus Timing Characteristics 3.3V Range 126 Appendix D Package Information Figure D-1 80-pin QFP Mechanical Dimensions case no B 80-pin QFP package Figure D-2 52-pin Lqfp Mechanical Dimensions case no D-03 52-pin Lqfp package 48-pin Lqfp package Section AE-AE Detail AD Appendix E Emulation Information 1 PK20 / XADDR1614 112-pin Lqfp package 134 Device User Guide End Sheet 136