Motorola MC9S12GC-Family System Clock Description, VDDA, Vssa Power Supply Pins for ATD and Vreg

Device User Guide — 9S12C128DGV1/D V01.05

2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG

VDDA, VSSA are the power supply and ground input pins for the voltage regulator reference and the analog to digital converter.

2.4.5 VRH, VRL — ATD Reference Voltage Input Pins

VRH and VRL are the reference voltage input pins for the analog to digital converter.

2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL

Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the supply voltage to the Oscillator and PLL to be bypassed independently. This 2.5V voltage is generated by the internal voltage regulator.

Table 2-2 MC9S12C-Family Power and Ground Connection Summary

Mnemonic	Nominal	Description
	Voltage
VDD1	2.5 V	Internal power and ground generated by internal regulator. These also
VDD2		allow an external source to supply the core VDD/VSS voltages and bypass
VSS1	0V	the internal voltage regulator.
VSS2		In the 48 and 52 LQFP packages VDD2 and VSS2 are not available.
VDDR	5.0 V	External power and ground, supply to internal voltage regulator.
VSSR	0 V
VDDX	5.0 V	External power and ground, supply to pin drivers.
VSSX	0 V
VDDA	5.0 V	Operating voltage and ground for the analog-to-digital converters and the
		reference for the internal voltage regulator, allows the supply voltage to the
VSSA	0 V
		A/D to be bypassed independently.
VRH	5.0 V	Reference voltage low for the ATD converter.
VRL	0 V	In the 48 and 52 LQFP packages VRL is bonded to VSSA.
VDDPLL	2.5 V	Provides operating voltage and ground for the Phased-Locked Loop. This
		allows the supply voltage to the PLL to be bypassed independently.
VSSPLL	0 V
		Internal power and ground generated by internal regulator.

NOTE:All VSS pins must be connected together in the application. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on MCU pin load.

Section 3 System Clock Description

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