Motorola MC9S12GC-Family warranty Table C-2 SPI Master Mode Timing Characteristics, Mosi Port Data

Device User Guide — 9S12C128DGV1/D V01.05

SS1
(OUTPUT)
	1
2
SCK
(CPOL = 0)
(OUTPUT)
4	4
SCK
(CPOL = 1)
(OUTPUT)
5	6
MISO	MSB IN2
(INPUT)
9

MOSI	PORT DATA	MASTER MSB OUT2
(OUTPUT)

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

12

12

BIT 6 . . . 1

11

BIT 6 . . . 1

13 3

13

LSB IN

MASTER LSB OUT PORT DATA

Figure C-2 SPI Master Timing (CPHA=1)

In Table C-2the timing characteristics for master mode are listed.

Table C-2 SPI Master Mode Timing Characteristics

Num	C	Characteristic			Symbol				Unit
						Min	Typ	Max
1	P	SCK Frequency			fsck	1/2048	—	1/2	fbus
1	P	SCK Period			tsck	2	—	2048	tbus
2	D	Enable Lead Time			tlead	—	1/2	—	tsck
3	D	Enable Lag Time			tlag	—	1/2	—	tsck
4	D	Clock (SCK) High or Low Time			twsck	—	1/2	—	tsck
5	D	Data Setup Time (Inputs)			tsu	8	—	—	ns
6	D	Data Hold Time (Inputs)			thi	8	—	—	ns
9	D	Data Valid after SCK Edge			tvsck	—	—	30	ns
10	D	Data Valid after		fall (CPHA=0)	tvss	—	—	15	ns
			SS
11	D	Data Hold Time (Outputs)			tho	20	—	—	ns
12	D	Rise and Fall Time Inputs			trfi	—	—	8	ns
13	D	Rise and Fall Time Outputs			trfo	—	—	8	ns

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