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Motorola MC9S12GC-Family warranty MC9S12C-Family Block Diagram

Models: MC9S12C-Family MC9S12GC-Family

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Device User Guide — 9S12C128DGV1/D V01.05

1.4 Block Diagram

Figure 1-1 MC9S12C-Family Block Diagram

VSSR

VDDR

VDDX

VSSX	Voltage Regulator

	VDD2	16K, 32K, 64K, 96K, 128K Byte Flash
	VSS2
	VDD1	1K, 2K, 4K Byte RAM
	VSS1	1K, 2K, 4K Byte RAM
	VSS1

ATD	VDDA
ATD	VSSA
	VRH
	VRL
	AN0
	AN1
	AN2	DDRAD	PTAD
	AN3	DDRAD	PTAD
	AN3
	AN4
	AN5
	AN6
	AN7

VDDA

VSSA

VRH

VRL

PAD0

PAD1

PAD2

PAD3

PAD4

PAD5

PAD6 PAD7

BKGD	MODC	Background	HCS12
	Debug12 Module		HCS12
	Debug12 Module		CPU
			CPU

	XFC
	VDDPLL		Clock and
	VSSPLL	PLL	Reset
	EXTAL	PLL	Generation	COP Watchdog
	EXTAL		Generation	COP Watchdog
	XTAL		Module	Clock Monitor
	XTAL			Clock Monitor
	RESET			Periodic Interrupt

IOC0

IOC1

IOC2

Timer IOC3

Module IOC4 IOC5

IOC6

IOC7

MUX

DDRT

PTT

PT0

PT1

PT2

PT3

PT4

PT5

PT6 PT7

	PE0			XIRQ
	PE1			IRQ	System
	PE2			R/W	System
	PE2	PTE	DDRE	R/W	Integration
	PE3			LSTRB/TAGLO	Integration
	PE4			ECLK	Module
	PE4			ECLK	(SIM)
	PE5			MODA/IPIPE0
	PE6			MODB/IPIPE1
	PE7			NOACC/XCLKS
	TEST/VPP

Multiplexed Address/Data Bus

		PW0	Keypad Interrupt
		PW1
	PWM	PW2		DDRP
	PWM	PW3			PTP
	Module	PW3
		PW4
		PW5

			Key Int	DDRJ	PTJ
	SCI	RXD		DDRS
	SCI	TXD			PTS
		TXD
	MSCAN is not available on the

PP0

PP1 PP2

PP3 PP4

PP5

PP6 PP7

PJ6 PJ7

PS0 PS1

PS2

DDRA

PTA

PA7	PA6	PA5	PA4	PA3	PA2	PA1	PA0
ADDR15	ADDR14	ADDR13	ADDR12	ADDR11	ADDR10	ADDR9	ADDR8

DDRB

PTB

PB7	PB6	PB5	PB4	PB3	PB2	PB1	PB0
ADDR7	ADDR6	ADDR5	ADDR4	ADDR3	ADDR2	ADDR1	ADDR0

9S12GC Family Members

	MSCAN	RXCAN
	MSCAN	TXCAN
	SPI	TXCAN	DDRM	PTM
	SPI	SS	DDRM	PTM
		MISO
		MOSI
		SCK

PS3

PM0

PM1

PM2

PM3

PM4 PM5

Multiplexed	DATA15 DATA14 DATA13 DATA12 DATA11 DATA10		DATA9 DATA8				DATA7	DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
Wide Bus
	Internal Logic 2.5V							I/O Driver 5V
	VDD1,2							VDDX
	VDD1,2							VDDX
	VSS1,2							VSSX

Signals shown in Bold are not available on the 52 or 48 Pin Package

Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package

PLL 2.5V

VDDPLL

VSSPLL

A/D Converter 5V						VRL is bonded internally to VSSA
VDDA						for 52 and 48 Pin packages
VDDA
VSSA

Voltage Regulator 5V & I/O

VDDR

VSSR

27

Image 27

Motorola MC9S12GC-Family warranty MC9S12C-Family Block Diagram

Contents

Document Number 9S12C128DGV1/D Device User Guide 9S12C128DGV1/D Revision HistoryTable of Contents System Clock Description Modes of Operation Resets and InterruptsVoltage Regulator Vreg Block Description HCS12 Core Block DescriptionAppendix B Electrical Specifications Appendix C Electrical Specifications Appendix D Package InformationAppendix E Emulation Information Device User Guide 9S12C128DGV1/D List of Figures Device User Guide 9S12C128DGV1/D List of Tables Device User Guide 9S12C128DGV1/D Device User Guide 9S12C128DGV1/D Device User Guide 9S12C128DGV1/D Package Device Part Number Mask Temp Flash PrefaceList of MC9S12C and MC9S12GC Family members MC9S12C-Family Package Option SummarySpeed Options 25 = 25MHz bus 16 = 16MHz bus Part Number Mask Temp Package Speed Description SetTBD 48LQFP MC9S12C96PVFA16 MC9S12C96PCFA16MC9S12C96PCPB16 MC9S12C96PCFU16MC9S12C64PCFA16 MC9S12C96PMFA25MC9S12C96PMPB25 MC9S12C96PMFU25MC9S12GC-Family Part Number Coding MC9S12GC64PVFA25 MC9S12GC64CFA25 TBDMC9S12GC64CPB25 TBD MC9S12GC64CFU25 TBDTerminology Document ReferencesUser Guide Version Document Order Number Device User Guide 9S12C128DGV1/D Features IntroductionOverview Device User Guide 9S12C128DGV1/D Modes of Operation Special Test ModeMotorola use only MC9S12C-Family Block Diagram Block DiagramDevice Memory Map Device Register Map OverviewAddress Module Size MC9S12C128 and MC9S12GC128 User configurable Memory Map MC9S12C96 User Configurable Memory Map MC9S12C64 and MC9S12GC64 User Configurable Memory Map MC9S12C32 and MC9S12GC32 User Configurable Memory Map Detailed Register Map MC9S12GC16 User Configurable Memory MapIvis $0010 $0014 MMC map 1 of 4 HCS12 Module Mapping ControlMiscellaneous Peripherals Device User Guide $0015 $0016 INT map 1 of 2 HCS12 Interrupt$0017 $0017 MMC map 2 of 4 HCS12 Module Mapping Control $0018 $0018$0020 $002F DBG including BKP map 1 of 1 HCS12 Debug $001F $001F INT map 2 of 2 HCS12 Interrupt$0030 $0031 MMC map 4 of 4 HCS12 Module Mapping Control $0034 $003F CRG Clock and Reset Generator$0040 $006F TIM Timer 16 Bit 8 Channels $0050 $0070 $007F Reserved $00A0 $00C7TIE $00C8 $00CF SCI Asynchronous Serial Interface$00D0 $00D7 Reserved $00D8 $00DF SPI Serial Peripheral Interface$00E0 $00FF PWM Pulse Width Modulator $0100 $010F Flash Control Register $0110 $013F $0140 $017F Reserved Can Motorola Scalable can MSCAN1Time $0140 $017F Can Motorola Scalable can MSCAN1 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 $0180 $023FReserved $0240 $027F PIM Port Interface Module PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0Ptis DDRAD2 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0PTIAD7 PTIAD6 PTIAD5 PTIAD4 PTIAD3 PTIAD2 PTIAD1 PTIJ7 DDRAD7Memory size registers Part ID Assignments$0280 $03FF Reserved space Assigned Part ID NumbersMC9S12C32, MC9S12GC32 Device Pinout Signal DescriptionPW4/IOC4/PT4 PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3Pin Assignments in 48 Lqfp for MC9S12C-Family Resistor Description Function Domain Signal Properties SummarySignal Properties Internal PullDevice User Guide 9S12C128DGV1/D Internal Pull Pin Name Pin Initialization for 48 & 52 Pin Lqfp bond-out versionsTest / VPP Test Pin Detailed Signal DescriptionsEXTAL, Xtal Oscillator Pins Reset External Reset Pin8 PE7 / Noacc / Xclks Port E I/O Pin Bkgd / Taghi / Modc Background Debug, Tag High & Mode Pin6 PA70 / ADDR158 / DATA158 Port a I/O Pins 7 PB70 / ADDR70 / DATA70 Port B I/O PinsPierce Oscillator Connections PE7=0 Colpitts Oscillator Connections PE7=112 PE3 / Lstrb Port E I/O Pin 3 / Low-Byte Strobe Lstrb 9 PE6 / Modb / IPIPE1 Port E I/O Pin10 PE5 / Moda / IPIPE0 Port E I/O Pin 11 PE4 / ECLK- Port E I/O Pin 4 / E-Clock Output18 PP6 / KWP6/ROMCTL Port P I/O Pin 16 PAD70 / AN70 Port AD I/O Pins14 PE1 / IRQ Port E input Pin 1 / Maskable Interrupt Pin 17 PP7 / KWP7 Port P I/O Pin22 PM4 / Mosi Port M I/O Pin 19 PP50 / KWP50 / PW50 Port P I/O Pins20 PJ76 / KWJ76 Port J I/O Pins 21 PM5 / SCK Port M I/O PinPower Supply Pins MC9S12C-Family Power and Ground Connection Summary VDDA, Vssa Power Supply Pins for ATD and Vreg5 VRH, VRL ATD Reference Voltage Input Pins VDDPLL, Vsspll Power Supply Pins for PLLModes of Operation Chip Configuration SummaryMode Selection SecurityClock Selection Based on PE7 Unsecuring the Microcontroller Low Power ModesSecuring the Microcontroller Operation of the Secured MicrocontrollerVectors Resets and InterruptsResets Device-specific information Reset Summary TableEffects of Reset HCS12 Core Block DescriptionDevice Specific Flash page Mapping Device Visible with Ppage contentsBDM alternate clock Extended Address Range Emulation Implications2 VDD1, VDD2, VSS1, VSS2 Voltage Regulator Vreg Block DescriptionRecommended Printed Circuit Board Layout VregenComponent Purpose Type Value Recommended External Component ValuesRecommended PCB Layout 48 Lqfp Recommended PCB Layout 52 Lqfp VSS2 Recommended PCB Layout 80 QFPRecommended PCB Layout for 48 Lqfp Pierce Oscillator Recommended PCB Layout for 52 Lqfp Pierce Oscillator Recommended PCB Layout for 80QFP Pierce Oscillator Clock Reset Generator CRG Block DescriptionSerial Communications Interface SCI Block Description Timer TIM Block DescriptionOscillator OSC Block Description Analog to Digital Converter ATD Block DescriptionMscan Block Description Flash Block DescriptionRAM Block Description Pulse Width Modulator PWM Block DescriptionDevice User Guide 9S12C128DGV1/D Parameter Classification Appendix a Electrical CharacteristicsPower Supply GeneralCurrent Injection PinsNum Rating Symbol Min Max Unit Absolute Maximum RatingsTable A-1 Absolute Maximum Ratings Operating Conditions Table A-3 ESD and Latch-Up Protection CharacteristicsModel Description Symbol Value Unit ESD Protection and Latch-up ImmunityPower Dissipation and Thermal Characteristics Rating Symbol Min Typ Max UnitTable A-4 Operating Conditions Pint = IDD ⋅ VDD + Iddpll ⋅ Vddpll + Idda ⋅ Vdda 9 I/O Characteristics Table A-5 Thermal Package Characteristics1Num Rating Symbol Min Typ Max Unit Table A-6 5V I/O Characteristics Num Rating Symbol Min Typ Table A-7 3.3V I/O CharacteristicsSupply Currents Measurement ConditionsAdditional Remarks Table A-8 Supply Current Characteristics for MC9S12C32 Stop Current 40 C 27 C Table B-1 Voltage Regulator Electrical Parameters Appendix B Electrical SpecificationsCharacteristic Symbol Min Typical Max Unit Voltage Regulator Operating ConditionsLVI Chip Power-up and LVI/LVR graphical explanationOutput Loads Resistive LoadsNum Characteristic Symbol Min Typical Max Unit Capacitive LoadsTable B-2 Voltage Regulator Capacitive Loads Device User Guide 9S12C128DGV1/D Table B-3 ATD Operating Characteristics ATD CharacteristicsATD Operating Characteristics In 5V Range ATD Operating Characteristics In 3.3V RangeSource capacitance Table B-4 ATD Operating CharacteristicsFactors influencing accuracy Source ResistanceCurrent injection Table B-5 ATD Electrical CharacteristicsTable B-7 ATD Conversion Performance ATD accuracy 5V RangeATD accuracy 3.3V Range Table B-6 ATD Conversion Performance1LSB Figure B-2 ATD Accuracy Definitions Row Programming NVM, Flash and EepromNVM timing Single Word ProgrammingTable B-8 NVM Timing Characteristics Sector EraseMass Erase NVM Reliability Table B-9 NVM Reliability Characteristics108 Startup Reset, Oscillator and PLLOscillator External ResetStop Recovery Pseudo Stop and Wait RecoveryPhase Locked Loop Table B-11 Oscillator CharacteristicsXFC Component Selection XFC Pin Figure B-3 Basic PLL functional diagramJitter Information ⋅ synr += max ⎜ ⋅ t nom Table B-12 PLL Characteristics 116 Num Rating Symbol Min Typ Max Table B-13 Mscan Wake-up Pulse Characteristics118 Description Value Unit Appendix C Electrical SpecificationsMaster Mode Table C-1 Measurement ConditionsLSB Master LSB OUT Table C-2 SPI Master Mode Timing CharacteristicsNum Characteristic Symbol Unit Min Typ Max Mosi Port DataSlave MSB Slave ModeInput SCK Input MisoSlave LSB OUT Table C-3 SPI Slave Mode Timing CharacteristicsNum Characteristic Symbol Unit Min Typ Mosi Input Slave MSB OUTPE2 Lstrb PE3 Noacc PE7 PIPO0 PIPO1, PE6,5 External Bus TimingGeneral Muxed Bus Timing Eclk PE4Pweh Table C-4 Expanded Bus Timing Characteristics 5V RangeTable C-5 Expanded Bus Timing Characteristics 3.3V Range 126 Appendix D Package Information 80-pin QFP package Figure D-1 80-pin QFP Mechanical Dimensions case no B52-pin Lqfp package Figure D-2 52-pin Lqfp Mechanical Dimensions case no D-03Section AE-AE Detail AD 48-pin Lqfp packageAppendix E Emulation Information 1 PK20 / XADDR1614 112-pin Lqfp package 134 Device User Guide End Sheet 136