Motorola MC9S12C-Family, MC9S12GC-Family warranty

Device User Guide — 9S12C128DGV1/D V01.05

List of Figures

Figure 0-1 Order Part number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 1-1MC9S12C-Family Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 1-2 MC9S12C128 and MC9S12GC128 User configurable Memory Map . . . . . . 29 Figure 1-3 MC9S12C96 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 1-4 MC9S12C64 and MC9S12GC64 User Configurable Memory Map. . . . . . . . 31 Figure 1-5 MC9S12C32 and MC9S12GC32 User Configurable Memory Map. . . . . . . . 32 Figure 1-6 MC9S12GC16 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . 33 Figure 2-1 Pin Assignments in 80 QFP for MC9S12C-Family . . . . . . . . . . . . . . . . . . . . 52 Figure 2-2 Pin assignments in 52 LQFP for MC9S12C-Family. . . . . . . . . . . . . . . . . . . . 53 Figure 2-3 Pin Assignments in 48 LQFP for MC9S12C-Family . . . . . . . . . . . . . . . . . . . 54 Figure 2-4 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 2-5 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 2-6 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 2-7 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 8-1 Recommended PCB Layout (48 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 8-2 Recommended PCB Layout (52 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 8-3 Recommended PCB Layout (80 QFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 8-4 Recommended PCB Layout for 48 LQFP Pierce Oscillator . . . . . . . . . . . . . 77 Figure 8-5 Recommended PCB Layout for 52 LQFP Pierce Oscillator . . . . . . . . . . . . . 78 Figure 8-6 Recommended PCB Layout for 80QFP Pierce Oscillator . . . . . . . . . . . . . . . 79 Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) . . . . . 96 Figure B-2 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure B-3 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure B-4 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure B-5 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure C-1 SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Figure C-2 SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure C-3 SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Figure C-4 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Figure C-5 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure D-180-pin QFP Mechanical Dimensions (case no. 841B) . . . . . . . . . . . . . . . . 128 Figure D-2 52-pin LQFP Mechanical Dimensions (case no. 848D-03) . . . . . . . . . . . . 129

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