Motorola MC9S12C-Family, MC9S12GC-Family warranty

Device User Guide — 9S12C128DGV1/D V01.05

And finally the frequency relationship is defined as

fVCO	⋅ (synr + 1)
		= 50
n = ------------ = 2
fref

With the above values the resistance can be calculated. The example is shown for a loop bandwidth fC=10kHz:

	2 ⋅ π ⋅ n ⋅ fC
R =		= 2*π*50*10kHz/(316.7Hz/Ω)=9.9kΩ=~10kΩ
	KΦ

The capacitance Cs can now be calculated as:

	2 ⋅ ζ2	≈ 0.516--------------
C =			;(ζ = 0.9)	= 5.19nF =~ 4.7nF
s	π ⋅ fC ⋅ R	fC ⋅ R

The capacitance Cp should be chosen in the range of:

Cs ⁄ 20 ≤ Cp ≤ Cs ⁄ 10 Cp = 470pF

B.6.3.2 Jitter Information

The basic functionality of the PLL is shown in Figure B-3. With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure B-4.

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