Signal Properties Summary, Internal Pull | Motorola MC9S12C-Family

Device User Guide — 9S12C128DGV1/D V01.05

2.2 Signal Properties Summary

Table 2-1 Signal Properties

Internal Pull

Pin Name

Pin Name

Pin Name

Power

Resistor

Description

Function 1

Function 2

Function 3

Domain

CTRL

Reset

State

EXTAL

—

—

VDDPLL

NA

NA

Oscillator pins

XTAL

—

—

VDDPLL

NA

NA

—

—

VDDX

None

None

External reset pin

RESET

XFC

—

—

VDDPLL

NA

NA

PLL loop ﬁlter pin

TEST

VPP

—

VSSX

NA

NA

Test pin only

BKGD

MODC

VDDX

Up

Up

Background debug, mode pin, tag signal high

TAGHI

PE7

NOACC

VDDX

PUCR

Up

Port E I/O pin, access, clock select

XCLKS

While

PE6

IPIPE1

MODB

VDDX

RESET

Port E I/O pin and pipe status

pin is low: Down

PE5

IPIPE0

MODA

VDDX

While RESET

Port E I/O pin and pipe status

pin is low: Down

PE4

ECLK

—

VDDX

PUCR

Mode

Port E I/O pin, bus clock output

Dep1

PE3

Mode

LSTRB

TAGLO

VDDX

PUCR

Port E I/O pin, low strobe, tag signal low

Dep(1)

Mode

PE2

R/W

—

VDDX

PUCR

Port E I/O pin, R/W in expanded modes

Dep(1)

PE1

—

VDDX

PUCR

Up

Port E input, external interrupt pin

IRQ

PE0

—

VDDX

PUCR

Up

Port E input, non-maskable interrupt pin

XIRQ

PA[7:3]

ADDR[15:1/

—

VDDX

PUCR

Disabled

Port A I/O pin & multiplexed address/data

DATA[15:1]

PA[2:1]

ADDR[10:9/

—

VDDX

PUCR

Disabled

Port A I/O pin & multiplexed address/data

DATA[10:9]

PA[0]

ADDR[8]/

—

VDDX

PUCR

Disabled

Port A I/O pin & multiplexed address/data

DATA[8]

PB[7:5]

ADDR[7:5]/

—

VDDX

PUCR

Disabled

Port B I/O pin & multiplexed address/data

DATA[7:5]

PB[4]

ADDR[4]/

—

VDDX

PUCR

Disabled

Port B I/O pin & multiplexed address/data

DATA[4]

PB[3:0]

ADDR[3:0]/

—

VDDX

PUCR

Disabled

Port B I/O pin & multiplexed address/data

DATA[3:0]

PAD[7:0]

AN[7:0]

—

VDDA

PERAD/P

Disabled

Port AD I/O pins and ATD inputs

PSAD

PP[7]

KWP[7]

—

VDDX

PERP/

Disabled

Port P I/O Pins and keypad wake-up

PPSP

PP[6]

KWP[6]

ROMCTL

VDDX

PERP/

Disabled

Port P I/O Pins, keypad wake-up and ROMON

PPSP

enable.

PP[5]

KWP[5]

PW5

VDDX

PERP/

Disabled

Port P I/O Pin, keypad wake-up, PW5 output

PPSP

PP[4:3]

KWP[4:3]

PW[4:3]

VDDX

PERP/

Disabled

Port P I/O Pin, keypad wake-up, PWM output

PPSP

55

Image 55

Motorola MC9S12C-Family, MC9S12GC-Family Signal Properties Summary, Internal Pull, Resistor Description Function Domain

Contents

Document Number 9S12C128DGV1/D Device User Guide 9S12C128DGV1/D Revision History Table of Contents System Clock Description Modes of Operation Resets and Interrupts Voltage Regulator Vreg Block Description HCS12 Core Block Description Appendix B Electrical Specifications Appendix D Package Information Appendix C Electrical SpecificationsAppendix E Emulation Information Device User Guide 9S12C128DGV1/D List of Figures Device User Guide 9S12C128DGV1/D List of Tables Device User Guide 9S12C128DGV1/D Device User Guide 9S12C128DGV1/D Device User Guide 9S12C128DGV1/D Package Device Part Number Mask Temp Flash PrefaceList of MC9S12C and MC9S12GC Family members MC9S12C-Family Package Option Summary Part Number Mask Temp Package Speed Description Set Speed Options 25 = 25MHz bus 16 = 16MHz busTBD 48LQFP MC9S12C96PVFA16 MC9S12C96PCFA16MC9S12C96PCPB16 MC9S12C96PCFU16 MC9S12C64PCFA16 MC9S12C96PMFA25MC9S12C96PMPB25 MC9S12C96PMFU25 MC9S12GC-Family Part Number Coding MC9S12GC64PVFA25 MC9S12GC64CFA25 TBDMC9S12GC64CPB25 TBD MC9S12GC64CFU25 TBD Document References TerminologyUser Guide Version Document Order Number Device User Guide 9S12C128DGV1/D Introduction FeaturesOverview Device User Guide 9S12C128DGV1/D Modes of Operation Special Test ModeMotorola use only MC9S12C-Family Block Diagram Block Diagram Device Register Map Overview Device Memory MapAddress Module Size MC9S12C128 and MC9S12GC128 User configurable Memory Map MC9S12C96 User Configurable Memory Map MC9S12C64 and MC9S12GC64 User Configurable Memory Map MC9S12C32 and MC9S12GC32 User Configurable Memory Map Detailed Register Map MC9S12GC16 User Configurable Memory Map Ivis $0010 $0014 MMC map 1 of 4 HCS12 Module Mapping Control Miscellaneous Peripherals Device User Guide $0015 $0016 INT map 1 of 2 HCS12 Interrupt$0017 $0017 MMC map 2 of 4 HCS12 Module Mapping Control $0018 $0018 $0020 $002F DBG including BKP map 1 of 1 HCS12 Debug $001F $001F INT map 2 of 2 HCS12 Interrupt $0030 $0031 MMC map 4 of 4 HCS12 Module Mapping Control $0034 $003F CRG Clock and Reset Generator $0040 $006F TIM Timer 16 Bit 8 Channels $0050 $0070 $007F Reserved $00A0 $00C7 TIE $00C8 $00CF SCI Asynchronous Serial Interface$00D0 $00D7 Reserved $00D8 $00DF SPI Serial Peripheral Interface $00E0 $00FF PWM Pulse Width Modulator $0100 $010F Flash Control Register $0140 $017F Reserved Can Motorola Scalable can MSCAN1 $0110 $013FTime $0140 $017F Can Motorola Scalable can MSCAN1 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 $0180 $023FReserved $0240 $027F PIM Port Interface Module PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 Ptis DDRAD2 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0PTIAD7 PTIAD6 PTIAD5 PTIAD4 PTIAD3 PTIAD2 PTIAD1 PTIJ7 DDRAD7 Memory size registers Part ID Assignments$0280 $03FF Reserved space Assigned Part ID Numbers MC9S12C32, MC9S12GC32 Device Pinout Signal Description PW4/IOC4/PT4 PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 Pin Assignments in 48 Lqfp for MC9S12C-Family Resistor Description Function Domain Signal Properties SummarySignal Properties Internal Pull Device User Guide 9S12C128DGV1/D Internal Pull Pin Name Pin Initialization for 48 & 52 Pin Lqfp bond-out versions Test / VPP Test Pin Detailed Signal DescriptionsEXTAL, Xtal Oscillator Pins Reset External Reset Pin 8 PE7 / Noacc / Xclks Port E I/O Pin Bkgd / Taghi / Modc Background Debug, Tag High & Mode Pin6 PA70 / ADDR158 / DATA158 Port a I/O Pins 7 PB70 / ADDR70 / DATA70 Port B I/O Pins Pierce Oscillator Connections PE7=0 Colpitts Oscillator Connections PE7=1 12 PE3 / Lstrb Port E I/O Pin 3 / Low-Byte Strobe Lstrb 9 PE6 / Modb / IPIPE1 Port E I/O Pin10 PE5 / Moda / IPIPE0 Port E I/O Pin 11 PE4 / ECLK- Port E I/O Pin 4 / E-Clock Output 18 PP6 / KWP6/ROMCTL Port P I/O Pin 16 PAD70 / AN70 Port AD I/O Pins14 PE1 / IRQ Port E input Pin 1 / Maskable Interrupt Pin 17 PP7 / KWP7 Port P I/O Pin 22 PM4 / Mosi Port M I/O Pin 19 PP50 / KWP50 / PW50 Port P I/O Pins20 PJ76 / KWJ76 Port J I/O Pins 21 PM5 / SCK Port M I/O Pin Power Supply Pins MC9S12C-Family Power and Ground Connection Summary VDDA, Vssa Power Supply Pins for ATD and Vreg5 VRH, VRL ATD Reference Voltage Input Pins VDDPLL, Vsspll Power Supply Pins for PLL Modes of Operation Chip Configuration Summary Security Mode SelectionClock Selection Based on PE7 Unsecuring the Microcontroller Low Power ModesSecuring the Microcontroller Operation of the Secured Microcontroller Vectors Resets and Interrupts Resets Device-specific information Reset Summary TableEffects of Reset HCS12 Core Block Description Device Specific Flash page Mapping Device Visible with Ppage contentsBDM alternate clock Extended Address Range Emulation Implications 2 VDD1, VDD2, VSS1, VSS2 Voltage Regulator Vreg Block DescriptionRecommended Printed Circuit Board Layout Vregen Component Purpose Type Value Recommended External Component Values Recommended PCB Layout 48 Lqfp Recommended PCB Layout 52 Lqfp VSS2 Recommended PCB Layout 80 QFP Recommended PCB Layout for 48 Lqfp Pierce Oscillator Recommended PCB Layout for 52 Lqfp Pierce Oscillator Recommended PCB Layout for 80QFP Pierce Oscillator Clock Reset Generator CRG Block Description Serial Communications Interface SCI Block Description Timer TIM Block DescriptionOscillator OSC Block Description Analog to Digital Converter ATD Block Description Mscan Block Description Flash Block DescriptionRAM Block Description Pulse Width Modulator PWM Block Description Device User Guide 9S12C128DGV1/D Parameter Classification Appendix a Electrical CharacteristicsPower Supply General Current Injection Pins Absolute Maximum Ratings Num Rating Symbol Min Max UnitTable A-1 Absolute Maximum Ratings Operating Conditions Table A-3 ESD and Latch-Up Protection CharacteristicsModel Description Symbol Value Unit ESD Protection and Latch-up Immunity Rating Symbol Min Typ Max Unit Power Dissipation and Thermal CharacteristicsTable A-4 Operating Conditions Pint = IDD ⋅ VDD + Iddpll ⋅ Vddpll + Idda ⋅ Vdda Table A-5 Thermal Package Characteristics1 9 I/O CharacteristicsNum Rating Symbol Min Typ Max Unit Table A-6 5V I/O Characteristics Num Rating Symbol Min Typ Table A-7 3.3V I/O Characteristics Measurement Conditions Supply CurrentsAdditional Remarks Table A-8 Supply Current Characteristics for MC9S12C32 Stop Current 40 C 27 C Table B-1 Voltage Regulator Electrical Parameters Appendix B Electrical SpecificationsCharacteristic Symbol Min Typical Max Unit Voltage Regulator Operating Conditions LVI Chip Power-up and LVI/LVR graphical explanationOutput Loads Resistive Loads Capacitive Loads Num Characteristic Symbol Min Typical Max UnitTable B-2 Voltage Regulator Capacitive Loads Device User Guide 9S12C128DGV1/D Table B-3 ATD Operating Characteristics ATD CharacteristicsATD Operating Characteristics In 5V Range ATD Operating Characteristics In 3.3V Range Source capacitance Table B-4 ATD Operating CharacteristicsFactors influencing accuracy Source Resistance Current injection Table B-5 ATD Electrical Characteristics Table B-7 ATD Conversion Performance ATD accuracy 5V RangeATD accuracy 3.3V Range Table B-6 ATD Conversion Performance 1LSB Figure B-2 ATD Accuracy Definitions Row Programming NVM, Flash and EepromNVM timing Single Word Programming Sector Erase Table B-8 NVM Timing CharacteristicsMass Erase NVM Reliability Table B-9 NVM Reliability Characteristics 108 Startup Reset, Oscillator and PLL Oscillator External ResetStop Recovery Pseudo Stop and Wait Recovery Table B-11 Oscillator Characteristics Phase Locked LoopXFC Component Selection XFC Pin Figure B-3 Basic PLL functional diagram Jitter Information ⋅ synr + = max ⎜ ⋅ t nom Table B-12 PLL Characteristics 116 Num Rating Symbol Min Typ Max Table B-13 Mscan Wake-up Pulse Characteristics 118 Description Value Unit Appendix C Electrical SpecificationsMaster Mode Table C-1 Measurement Conditions LSB Master LSB OUT Table C-2 SPI Master Mode Timing CharacteristicsNum Characteristic Symbol Unit Min Typ Max Mosi Port Data Slave MSB Slave ModeInput SCK Input Miso Slave LSB OUT Table C-3 SPI Slave Mode Timing CharacteristicsNum Characteristic Symbol Unit Min Typ Mosi Input Slave MSB OUT PE2 Lstrb PE3 Noacc PE7 PIPO0 PIPO1, PE6,5 External Bus TimingGeneral Muxed Bus Timing Eclk PE4 Pweh Table C-4 Expanded Bus Timing Characteristics 5V Range Table C-5 Expanded Bus Timing Characteristics 3.3V Range 126 Appendix D Package Information 80-pin QFP package Figure D-1 80-pin QFP Mechanical Dimensions case no B 52-pin Lqfp package Figure D-2 52-pin Lqfp Mechanical Dimensions case no D-03 Section AE-AE Detail AD 48-pin Lqfp package Appendix E Emulation Information 1 PK20 / XADDR1614 112-pin Lqfp package 134 Device User Guide End Sheet 136