Motorola MC9S12C-Family, MC9S12GC-Family External Bus Timing, General Muxed Bus Timing, Eclk PE4

Device User Guide — 9S12C128DGV1/D V01.05

C.3 External Bus Timing

A timing diagram of the external multiplexed-bus is illustrated in Figure C-5with the actual timing values shown on table Table C-4. All major bus signals are included in the diagram. While both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle.

C.3.1 General Muxed Bus Timing

The expanded bus timings are highly dependent on the load conditions. The timing parameters shown assume a balanced load across all outputs.

Figure C-5 General External Bus Timing

ECLK

PE4

Addr/Data

(read) PA, PB

Addr/Data

(write) PA, PB

R/W

PE2

LSTRB

PE3

NOACC

PE7

PIPO0 PIPO1, PE6,5

	1, 2
	3		4
5	6	16	10	11
9	15
data	addr		data
		7	8
	12		14	13
data	addr		data
17	18			19
20	21			22
23	24			25
26	27	28	29

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