Motorola MC9S12C-Family, MC9S12GC-Family warranty Modes of Operation, Chip Configuration Summary

Device User Guide — 9S12C128DGV1/D V01.05

The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1shows the clock connections from the CRG to all modules. Consult the CRG Block User Guide for details on clock generation.

EXTAL

CRG

XTAL

	S12_CORE
	core clock
	Flash
	RAM
	TIM
	ATD
	PIM
	SCI
bus clock	SPI
oscillator clock	MSCAN
	Not on 9S12GC
	VREG
	TPM

Figure 3-1 Clock Connections

Section 4 Modes of Operation

4.1 Overview

Eight possible modes determine the operating configuration of the MC9S12C Family. Each mode has an associated default memory map and external bus configuration controlled by a further pin.

Three low power modes exist for the device.

4.2 Chip Configuration Summary

The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset. The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are

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