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Motorola MC9S12C-Family, MC9S12GC-Family warranty Resets

Models: MC9S12C-Family MC9S12GC-Family

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Device User Guide — 9S12C128DGV1/D V01.05

	$FFF6, $FFF7	SWI	None	None	–

	$FFF4, $FFF5	XIRQ	X-Bit	None	–

	$FFF2, $FFF3	IRQ	I-Bit	INTCR (IRQEN)	$F2

	$FFF0, $FFF1	Real Time Interrupt	I-Bit	CRGINT (RTIE)	$F0

	$FFEE, $FFEF	Standard Timer channel 0	I-Bit	TIE (C0I)	$EE

	$FFEC, $FFED	Standard Timer channel 1	I-Bit	TIE (C1I)	$EC

	$FFEA, $FFEB	Standard Timer channel 2	I-Bit	TIE (C2I)	$EA

	$FFE8, $FFE9	Standard Timer channel 3	I-Bit	TIE (C3I)	$E8

	$FFE6, $FFE7	Standard Timer channel 4	I-Bit	TIE (C4I)	$E6

	$FFE4, $FFE5	Standard Timer channel 5	I-Bit	TIE (C5I)	$E4

	$FFE2, $FFE3	Standard Timer channel 6	I-Bit	TIE (C6I)	$E2

	$FFE0, $FFE1	Standard Timer channel 7	I-Bit	TIE (C7I)	$E0

	$FFDE, $FFDF	Standard Timer overﬂow	I-Bit	TMSK2 (TOI)	$DE

	$FFDC, $FFDD	Pulse accumulator A overﬂow	I-Bit	PACTL (PAOVI)	$DC

	$FFDA, $FFDB	Pulse accumulator input edge	I-Bit	PACTL (PAI)	$DA

	$FFD8, $FFD9	SPI	I-Bit	SPICR1 (SPIE, SPTIE)	$D8

	$FFD6, $FFD7	SCI	I-Bit	SCICR2	$D6
	$FFD6, $FFD7	SCI	I-Bit	(TIE, TCIE, RIE, ILIE)	$D6
				(TIE, TCIE, RIE, ILIE)

	$FFD4, $FFD5		Reserved
	$FFD2, $FFD3	ATD	I-Bit	ATDCTL2 (ASCIE)	$D2

	$FFD0, $FFD1		Reserved
	$FFCE, $FFCF	Port J	I-Bit	PIEP (PIEP7-6)	$CE

	$FFCC, $FFCD		Reserved
	$FFCA, $FFCB		Reserved
	$FFC8, $FFC9		Reserved
	$FFC6, $FFC7	CRG PLL lock	I-Bit	PLLCR (LOCKIE)	$C6

	$FFC4, $FFC5	CRG Self Clock Mode	I-Bit	PLLCR (SCMIE)	$C4

	$FFBA to $FFC3		Reserved
	$FFB8, $FFB9	FLASH	I-Bit	FCNFG (CCIE, CBEIE)	$B8

	$FFB6, $FFB7	CAN wake-up1	I-Bit	CANRIER (WUPIE)	$B6
	$FFB4, $FFB5	CAN errors1	I-Bit	CANRIER (CSCIE, OVRIE)	$B4
	$FFB2, $FFB3	CAN receive1	I-Bit	CANRIER (RXFIE)	$B2
	$FFB0, $FFB1	CAN transmit1	I-Bit	CANTIER (TXEIE[2:0])	$B0
	$FF90 to $FFAF		Reserved
	$FF8E, $FF8F	Port P	I-Bit	PIEP (PIEP7-0)	$8E

	$FF8C, $FF8D	PWM Emergency Shutdown	I-Bit	PWMSDN(PWMIE)	$8C

	$FF8A, $FF8B	VREG LVI	I-Bit	CTRL0 (LVIE)	$8A

	$FF80 to $FF89		Reserved
	NOTES:

1.Not available on MC9S12GC-Family members

5.3Resets

Resets are a subset of the interrupts featured inTable 5-1. The different sources capable of generating a system reset are summarized in Table 5-2. When a reset occurs, MCU registers and control bits are

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Motorola MC9S12C-Family, MC9S12GC-Family warranty Resets

Contents

Document Number 9S12C128DGV1/D Device User Guide 9S12C128DGV1/D Revision HistoryTable of Contents System Clock Description Modes of Operation Resets and InterruptsVoltage Regulator Vreg Block Description HCS12 Core Block DescriptionAppendix B Electrical Specifications Appendix C Electrical Specifications Appendix D Package InformationAppendix E Emulation Information Device User Guide 9S12C128DGV1/D List of Figures Device User Guide 9S12C128DGV1/D List of Tables Device User Guide 9S12C128DGV1/D Device User Guide 9S12C128DGV1/D Device User Guide 9S12C128DGV1/D List of MC9S12C and MC9S12GC Family members PrefaceMC9S12C-Family Package Option Summary Package Device Part Number Mask Temp FlashSpeed Options 25 = 25MHz bus 16 = 16MHz bus Part Number Mask Temp Package Speed Description SetTBD 48LQFP MC9S12C96PCPB16 MC9S12C96PCFA16MC9S12C96PCFU16 MC9S12C96PVFA16MC9S12C96PMPB25 MC9S12C96PMFA25MC9S12C96PMFU25 MC9S12C64PCFA16MC9S12GC-Family Part Number Coding MC9S12GC64CPB25 TBD MC9S12GC64CFA25 TBDMC9S12GC64CFU25 TBD MC9S12GC64PVFA25Terminology Document ReferencesUser Guide Version Document Order Number Device User Guide 9S12C128DGV1/D Features IntroductionOverview Device User Guide 9S12C128DGV1/D Modes of Operation Special Test ModeMotorola use only MC9S12C-Family Block Diagram Block DiagramDevice Memory Map Device Register Map OverviewAddress Module Size MC9S12C128 and MC9S12GC128 User configurable Memory Map MC9S12C96 User Configurable Memory Map MC9S12C64 and MC9S12GC64 User Configurable Memory Map MC9S12C32 and MC9S12GC32 User Configurable Memory Map Detailed Register Map MC9S12GC16 User Configurable Memory MapIvis $0010 $0014 MMC map 1 of 4 HCS12 Module Mapping Control$0017 $0017 MMC map 2 of 4 HCS12 Module Mapping Control $0015 $0016 INT map 1 of 2 HCS12 Interrupt$0018 $0018 Miscellaneous Peripherals Device User Guide$0020 $002F DBG including BKP map 1 of 1 HCS12 Debug $001F $001F INT map 2 of 2 HCS12 Interrupt$0030 $0031 MMC map 4 of 4 HCS12 Module Mapping Control $0034 $003F CRG Clock and Reset Generator$0040 $006F TIM Timer 16 Bit 8 Channels $0050 $0070 $007F Reserved $00A0 $00C7$00D0 $00D7 $00C8 $00CF SCI Asynchronous Serial InterfaceReserved $00D8 $00DF SPI Serial Peripheral Interface TIE$00E0 $00FF PWM Pulse Width Modulator $0100 $010F Flash Control Register $0110 $013F $0140 $017F Reserved Can Motorola Scalable can MSCAN1Time $0140 $017F Can Motorola Scalable can MSCAN1 Reserved $0240 $027F PIM Port Interface Module $0180 $023FPRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0Ptis PTIAD7 PTIAD6 PTIAD5 PTIAD4 PTIAD3 PTIAD2 PTIAD1 PTIJ7 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0DDRAD7 DDRAD2$0280 $03FF Reserved space Part ID AssignmentsAssigned Part ID Numbers Memory size registersMC9S12C32, MC9S12GC32 Device Pinout Signal DescriptionPW4/IOC4/PT4 PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3Pin Assignments in 48 Lqfp for MC9S12C-Family Signal Properties Signal Properties SummaryInternal Pull Resistor Description Function DomainDevice User Guide 9S12C128DGV1/D Internal Pull Pin Name Pin Initialization for 48 & 52 Pin Lqfp bond-out versionsEXTAL, Xtal Oscillator Pins Detailed Signal DescriptionsReset External Reset Pin Test / VPP Test Pin6 PA70 / ADDR158 / DATA158 Port a I/O Pins Bkgd / Taghi / Modc Background Debug, Tag High & Mode Pin7 PB70 / ADDR70 / DATA70 Port B I/O Pins 8 PE7 / Noacc / Xclks Port E I/O PinPierce Oscillator Connections PE7=0 Colpitts Oscillator Connections PE7=110 PE5 / Moda / IPIPE0 Port E I/O Pin 9 PE6 / Modb / IPIPE1 Port E I/O Pin11 PE4 / ECLK- Port E I/O Pin 4 / E-Clock Output 12 PE3 / Lstrb Port E I/O Pin 3 / Low-Byte Strobe Lstrb14 PE1 / IRQ Port E input Pin 1 / Maskable Interrupt Pin 16 PAD70 / AN70 Port AD I/O Pins17 PP7 / KWP7 Port P I/O Pin 18 PP6 / KWP6/ROMCTL Port P I/O Pin20 PJ76 / KWJ76 Port J I/O Pins 19 PP50 / KWP50 / PW50 Port P I/O Pins21 PM5 / SCK Port M I/O Pin 22 PM4 / Mosi Port M I/O PinPower Supply Pins 5 VRH, VRL ATD Reference Voltage Input Pins VDDA, Vssa Power Supply Pins for ATD and VregVDDPLL, Vsspll Power Supply Pins for PLL MC9S12C-Family Power and Ground Connection SummaryModes of Operation Chip Configuration SummaryMode Selection SecurityClock Selection Based on PE7 Securing the Microcontroller Low Power ModesOperation of the Secured Microcontroller Unsecuring the MicrocontrollerVectors Resets and InterruptsResets Effects of Reset Reset Summary TableHCS12 Core Block Description Device-specific informationBDM alternate clock Device Visible with Ppage contentsExtended Address Range Emulation Implications Device Specific Flash page MappingRecommended Printed Circuit Board Layout Voltage Regulator Vreg Block DescriptionVregen 2 VDD1, VDD2, VSS1, VSS2Component Purpose Type Value Recommended External Component ValuesRecommended PCB Layout 48 Lqfp Recommended PCB Layout 52 Lqfp VSS2 Recommended PCB Layout 80 QFPRecommended PCB Layout for 48 Lqfp Pierce Oscillator Recommended PCB Layout for 52 Lqfp Pierce Oscillator Recommended PCB Layout for 80QFP Pierce Oscillator Clock Reset Generator CRG Block DescriptionOscillator OSC Block Description Timer TIM Block DescriptionAnalog to Digital Converter ATD Block Description Serial Communications Interface SCI Block DescriptionRAM Block Description Flash Block DescriptionPulse Width Modulator PWM Block Description Mscan Block DescriptionDevice User Guide 9S12C128DGV1/D Power Supply Appendix a Electrical CharacteristicsGeneral Parameter ClassificationCurrent Injection PinsNum Rating Symbol Min Max Unit Absolute Maximum RatingsTable A-1 Absolute Maximum Ratings Model Description Symbol Value Unit Table A-3 ESD and Latch-Up Protection CharacteristicsESD Protection and Latch-up Immunity Operating ConditionsPower Dissipation and Thermal Characteristics Rating Symbol Min Typ Max UnitTable A-4 Operating Conditions Pint = IDD ⋅ VDD + Iddpll ⋅ Vddpll + Idda ⋅ Vdda 9 I/O Characteristics Table A-5 Thermal Package Characteristics1Num Rating Symbol Min Typ Max Unit Table A-6 5V I/O Characteristics Num Rating Symbol Min Typ Table A-7 3.3V I/O CharacteristicsSupply Currents Measurement ConditionsAdditional Remarks Table A-8 Supply Current Characteristics for MC9S12C32 Stop Current 40 C 27 C Characteristic Symbol Min Typical Max Unit Appendix B Electrical SpecificationsVoltage Regulator Operating Conditions Table B-1 Voltage Regulator Electrical ParametersOutput Loads Chip Power-up and LVI/LVR graphical explanationResistive Loads LVINum Characteristic Symbol Min Typical Max Unit Capacitive LoadsTable B-2 Voltage Regulator Capacitive Loads Device User Guide 9S12C128DGV1/D ATD Operating Characteristics In 5V Range ATD CharacteristicsATD Operating Characteristics In 3.3V Range Table B-3 ATD Operating CharacteristicsFactors influencing accuracy Table B-4 ATD Operating CharacteristicsSource Resistance Source capacitanceCurrent injection Table B-5 ATD Electrical CharacteristicsATD accuracy 3.3V Range ATD accuracy 5V RangeTable B-6 ATD Conversion Performance Table B-7 ATD Conversion Performance1LSB Figure B-2 ATD Accuracy Definitions NVM timing NVM, Flash and EepromSingle Word Programming Row ProgrammingTable B-8 NVM Timing Characteristics Sector EraseMass Erase NVM Reliability Table B-9 NVM Reliability Characteristics108 Startup Reset, Oscillator and PLLStop Recovery External ResetPseudo Stop and Wait Recovery OscillatorPhase Locked Loop Table B-11 Oscillator CharacteristicsXFC Component Selection XFC Pin Figure B-3 Basic PLL functional diagramJitter Information ⋅ synr += max ⎜ ⋅ t nom Table B-12 PLL Characteristics 116 Num Rating Symbol Min Typ Max Table B-13 Mscan Wake-up Pulse Characteristics118 Master Mode Appendix C Electrical SpecificationsTable C-1 Measurement Conditions Description Value UnitNum Characteristic Symbol Unit Min Typ Max Table C-2 SPI Master Mode Timing CharacteristicsMosi Port Data LSB Master LSB OUTInput SCK Slave ModeInput Miso Slave MSBNum Characteristic Symbol Unit Min Typ Table C-3 SPI Slave Mode Timing CharacteristicsMosi Input Slave MSB OUT Slave LSB OUTGeneral Muxed Bus Timing External Bus TimingEclk PE4 PE2 Lstrb PE3 Noacc PE7 PIPO0 PIPO1, PE6,5Pweh Table C-4 Expanded Bus Timing Characteristics 5V RangeTable C-5 Expanded Bus Timing Characteristics 3.3V Range 126 Appendix D Package Information 80-pin QFP package Figure D-1 80-pin QFP Mechanical Dimensions case no B52-pin Lqfp package Figure D-2 52-pin Lqfp Mechanical Dimensions case no D-03Section AE-AE Detail AD 48-pin Lqfp packageAppendix E Emulation Information 1 PK20 / XADDR1614 112-pin Lqfp package 134 Device User Guide End Sheet 136