Motorola MC9S12C-Family, MC9S12GC-Family warranty Reset, Oscillator and PLL

Device User Guide — 9S12C128DGV1/D V01.05

B.6 Reset, Oscillator and PLL

This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL).

B.6.1 Startup

Table B-10 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.

Table B-10 Startup Characteristics

Conditions are shown in Table A-4 unless otherwise noted

Num	C	Rating			Symbol	Min	Typ	Max	Unit
1	T	POR release level			VPORR			2.07	V
2	T	POR assert level			VPORA	0.97			V
3	D	Reset input pulse width, minimum input time			PWRSTL	2			tosc
4	D	Startup from Reset			nRST	192		196	nosc
		Interrupt pulse width,		edge-sensitive
5	D		IRQ		PWIRQ	20			ns
		mode
6	D	Wait recovery startup time			tWRS			14	tcyc

B.6.1.1 POR

The release level VPORR and the assert level VPORA are derived from the VDD Supply. They are also valid if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check

are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc.

B.6.1.2 LVR

The release level VLVRR and the assert level VLVRA are derived from the VDD Supply. They are also valid if the device is powered externally. After releasing the LVR reset the oscillator and the clock quality check

are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc.

B.6.1.3 SRAM Data Retention

Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set.

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