Manuals / Motorola / Computer Equipment / Computer Hardware

Motorola MVME1X7P manual Tblsc, ROM0

Models: MVME1X7P

1 316

Download 316 pages 46.44 Kb

Page 144

2

VMEchip2

TBLSC

These bits control the snoop signal lines on the local bus

when the DMAC is table walking. The snooping functions

differ according to processor type, as shown:

TBLSC

Requested Snoop Operation

19

18

MC68040

MC68060

0

0

Snoop disabled

Snoop enabled

0

1

Source dirty, sink byte/word/longword

Snoop disabled

1

0

Source dirty, invalidate line

Snoop enabled

1

1

Snoop disabled (Reserved)

Snoop disabled

ROM0

This bit is not used on the MVME1x7P. Its function is

performed by the ROM0 bit in the Petra/MC2 PROM

Access Time Control register. Refer to Chapter 3.

WAIT RMW This function is not used on the MVME1x7P.

Local-Bus-to-VMEbus Requester Control Register

ADR/SIZ

$FFF40030 (8 bits [7 used] OF 32)

BIT

15

14

13

12

11

10

9

8

NAME

ROBN

DHB

DWB

LVFAIR

LVRWD

LVREQL

OPER

R/W

R

R/W

R/W

R/W

R/W

RESET

0 PS

0 PS

0 PSL

0 PS

0 PS

0 PS

This register controls the VMEbus request level, the request mode, and release mode for the local-bus-to-VMEbus interface.

LVREQL These bits define the VMEbus request level. The request level can only change while the VMEchip2 is bus master. The VMEchip2 always requests at the old level until it becomes bus master and the new level takes effect. If the VMEchip2 is bus master when the level is changed, the new level does not take effect until the bus has been released and re-requested at the old level. The requester always requests the VMEbus at level 3 the first time following a SYSRESET.

2-54	Computer Group Literature Center Web Site

Image 144

Motorola MVME1X7P manual Tblsc, ROM0

Contents

Programmer’s Reference Guide MVME1X7P Single-Board ComputerPage Safety Summary Flammability CE Notice European Community Limited and Restricted Rights Legend Contents Viii VMEchip2 Page Page PCCchip2 Xiii Chapter Appendix a Summary of Changes Xvi List of Figures Xviii List of Tables Page Model Number Characteristics About This ManualOverview of Contents Comments and SuggestionsConventions Used in This Manual CR represents the carriage return or Enter key CtrlXxv Xxvi Introduction Petra Asic and Second-Generation MVME1X7 BoardsProgramming Issues Features MVME1X7P Features SummaryFeature Block Diagram Applicable Industry StandardsMVME167P Block Diagram MVME177P Block Diagram Programming Interfaces Data Bus StructureEEPROMs on the MVME1X7P Model Sockets BanksFlash Memory on the MVME177 MVME177Sram Onboard Sdram Battery-Backed-Up RAM and Clock VMEbus InterfaceInterfaces Serial Port Interface Parallel Printer Interface Ethernet Interface Programmable Tick Timers Local ResourcesScsi Interface Watchdog Timer Local Bus TimeoutFunctional Description Software-Programmable Hardware InterruptsVMEbus Interface and VMEchip2 VMEchip2 General-Purpose I/OPetra/VMEchip2 Redundant Logic Functions Duplicated in VMEchip2 and Petra ASICs VMEchip2 Petra Chip Address Bit #Memory Maps Local Bus Memory MapNormal Address Range Local Bus Memory Map Address Range Devices Accessed Port Size Local I/O Devices Memory Map3KB Programming Issues Detailed I/O Memory Maps Tables 1-5 through 1-14 give the detailed memory maps forVMEchip2 Memory Map Sheet 1 OffsetThis sheet begins on facing VMEchip2 Memory Map Sheet 2 PRECompare Register Counter Overflow VMEchip2 Memory Map Sheet 3 Offsets Bit NumbersPrinter Memory Map PCCchip2 Memory Map SCC Transmit PiackVector Base Register Mcecc Internal Register Memory Map Mcecc Base Address = $FFF43000 1st $FFF43100 2ndRegister Bit Names D31 D30 D29 D28 D27 D26 D25 D24Register Register Bit Names Cirrus Logic CD2401 Serial Port Memory Map Option RegistersChannel Command and Status Registers Interrupt RegistersReceive Interrupt Registers Transmit Interrupt Registers Modem Interrupt RegistersDMA Registers DMA Receive RegistersTimer Registers DMA Transmit Registers10 CA Ethernet LAN Memory Map 11 C710 Scsi Memory Map BBRAM/TOD Clock Memory Map13. Bbram Configuration Area Memory Map 12. M48T58 BBRAM,TOD Clock Memory MapAddress Range Description Size Bytes 14. TOD Clock Memory Map Address Data Bits FunctionMVME167P-24SE 01-W3620F35C VMEbus Accesses to the Local Bus VMEbus Memory MapInterrupt Acknowledge Map VMEbus Short I/O Memory MapExample VMEchip2 Tick Timer 1 Periodic Interrupt Interrupt HandlingTo the Tick Timer 1 Compare Register description Cache Coherency MVME167P Cache Coherency MVME177P Using Bus Timers Indivisible Cycles 15. Single-Cycle InstructionsInstructions Supervisor Stack Pointer MC68060 Sources of Local Bus Errors Local Bus TimeoutVMEbus Access Timeout VMEbus BerrError Conditions Bus Error ProcessingVMEchip2 MPU Parity Error MPU Offboard ErrorMPU TEA Cause Unidentified Dmac VMEbus Error Dmac Parity ErrorMPU Local Bus Time-out Dmac Offboard Error Dmac LTO ErrorSCC Retry Error Dmac TEA Cause UnidentifiedSCC Parity Error SCC Offboard ErrorSCC LTO Error LAN Parity ErrorLAN Offboard Error LAN LTO Error Scsi Parity ErrorScsi Offboard Error Scsi LTO Error Programming Issues Computer Group Literature Center Web Site Features of the VMEchip2 Asic Function FeaturesVMEchip2 Introduction Functional Blocks Local-Bus-to-VMEbus InterfaceVMEchip2 Block Diagram VMEchip2 Local-Bus-to-VMEbus Requester VMEchip2 VMEbus-to-Local-Bus Interface Functional BlocksLocal-Bus-to-VMEbus DMA Controller Functional Blocks No-Address-Increment DMA Transfers Dmac VMEbus Requester Tick and Watchdog Timers PrescalerTick Timers VMEbus Interrupter Bus Timer VMEbus System ControllerArbiter Iack Daisy-Chain DriverReset Driver Local Bus Interrupter and Interrupt HandlerDmac done VMEbus Sysfail interrupterFunctional Blocks Lcsr Programming Model Global Control and Status RegistersState of the bit following a reset, defined as follows 2shows a summary of the LCSRsVMEchip2 Memory Map-LCSR Summary Sheet 1 IO2 IO1 VMEchip2 Memory Map-LCSR Summary Sheet 2 IRQ7 IRQ6 IRQ5 Programming the VMEbus Slave Map Decoders Lcsr Programming Model VMEbus Slave Ending Address Register VMEbus Slave Starting Address RegisterLocal-bus map decoder VMEbus Slave Address Translation Address Offset RegisterVMEbus Slave Address Translation Select Register Segment Address Translation Size Select Value$FFF4000C 16 bits VMEbus Slave Write Post and Snoop Control Register WP2SNP2 VMEbus Slave Address Modifier Select Register DATPGM BLKUSR SUPWP1 SNP1When this bit is high, the first map decoder responds to Block access cyclesA24 access cycles CyclesA32 access cycles VMEbus supervisory access cycles. When this bit is lowProgramming the Local-Bus-to-VMEbus Map Decoders Bit is low, the first map decoder does not respond toVMEchip2 Local Bus Slave VMEbus Master Ending Address Register Local Bus Slave VMEbus Master Starting Address Register $FFF4001C 16 bits $FFF40024 16 bits Local Bus Slave VMEbus Master Attribute Register Segment defined by map decoder 3. When this bit is Decoder 3. Because the local-bus-to-VMEbus interfaceSegment defined by map decoder 2. When this bit is Decoder 2. Since the local-bus-to-VMEbus interface doesNot support block transfers, the block transfer address Segment defined by map decoder 1. When this bit is Decoder 1. Because the local-bus-to-VMEbus interfaceVMEbus Slave Gcsr Group Address Register VMEbus Slave Gcsr Board Address Register Local-Bus-to-VMEbus Enable Control Register EN1EN2 EN3Local-Bus-to-VMEbus I/O Control Register Programming the VMEchip2 DMA Controller I2WPI2EN ROM Control RegisterVMEchip2 Dmac Command Packet Format Dmac RegistersEprom Decoder, Sram and DMA Control Register Entry FunctionTblsc ROM0Lvrwd LvfairDWB DHBDrelm DfairDtbl DENDmac Control Register 2 bits TvmeLinc VincThis bit is used only in command chaining mode. It is only Modified when the Dmac loads the control register fromControl word in the command packet. When this bit SNPDmac Local Bus Address Counter Dmac VMEbus Address Counter Dmac Byte CounterTable Address Counter Dmac VMEbus Address CounterVMEbus Interrupter Control Register IrqlIrqs IrqcVMEbus Interrupter Vector Register MPU Status and DMA Interrupt Count RegisterDmac Status Register Programming the Tick and Watchdog Timers VMEbus Arbiter Time-Out Control RegisterVgto Time onLbto VatoPrescaler Control Register Prescaler register = 256- Bclock MHzTick Timer 1 Compare Register Tick Timer 1 CounterTick Timer 2 Compare Register Tick Timer 2 CounterTick timer 2 Counter Board Control Register Watchdog Timer Control Register WdenWDS/L Tick Timer 2 Control Register Tick Timer 1 Control Register Prescaler CounterProgramming the Local Bus Interrupter Local Bus Interrupter Summary Interrupt Vector Priority for Simultaneous InterruptsDmac Local Bus Interrupter Status Register bits LM0 LM1SIG0 SIG1SW0 SW1SW2 SW3VME1 VME2VME3 VME4Local Bus Interrupter Enable Register bits ELM0 ELM1ESIG0 ESIG1ESW0 ESW1ESW2 ESW3EIRQ1 EIRQ2EIRQ3 EIRQ4Software Interrupt Set Register bits Interrupt Clear Register bits Interrupt Level Register 1 bits IRQ1E Level These bits define the level of the tick timer 1 interrupt These bits define the level of the tick timer 2 interruptInterrupt Level Register 2 bits SIG3 Level SIG2 Level Interrupt Level Register 3 bits SW5 Level SW4 Level Interrupt Level Register 4 bits VIRQ7 LevelThese bits define the level of the VMEbus IRQ7 interrupt Spare LevelInterrupts may be mapped to any local bus interrupt level VIRQ3 LevelThese bits define the level of the VMEbus IRQ3 interrupt VIRQ4 LevelVIRQ1 Level VIRQ2 LevelVBR Control Register Connects to pin 16 of the Remote Status and Control Connects to pin 17 of the Remote Status and ControlConnects to pin 18 of the Remote Status and Control Not usedMiscellaneous Control Register EnintLcsr Programming Model Gcsr Programming Model 101 Programming the Gcsr 5shows a summary of the Gcsr VMEchip2 Memory Map Gcsr SummaryVMEchip2 Revision Register Offsets Bit Numbers LocaVMEchip2 ID Register VMEchip2 LM/SIG RegisterLM2 LM3VMEchip2 Board Status/Control Register ISFRST General Purpose Register Local Bus $FFF40114/VMEbus $XXYA 16 bits Summary of Major Features PCCchip2PCCchip2 Block Diagram General DescriptionBbram Interface 82596CA LAN Controller InterfaceMPU Port and MPU Channel Attention Lanc Bus Error MC68040-Bus Master Support for 82596CALanc Interrupt 53C710 Scsi Controller Interface Parallel Port InterfaceGeneral Purpose I/O Pin CD2401 SCC InterfacePCCchip2 Tick Timer Overall Memory Map PCCchip2 Devices Memory MapAddress Range Selected Device Comments Programming Model Summary of the PCCchip2 CSR is shown in TablePCCchip2 Memory Map Control and Status Registers Fast Chip ID Register Chip Revision RegisterGeneral Control Register FastVector Base Register DR0Interrupt Source IV3-IV0 Priority Gpio IRQProgramming the Tick Timers Tick Timer 2 Compare Register Prescaler Clock Adjust Register Prescaler Count RegisterPrescaler clock adjust register = 256 Bclk MHz Clear On Compare. When this bit is high, the counter is When this bit is low, the counter is not resetCEN $FFF42017 8 bits General Purpose Input Interrupt Control Register IclrIEN INTTick Timer 2 Interrupt Control Register General Purpose Input/Output Pin Control RegisterGPO GpoeInterrupt Status. When this bit is high a Tick Timer Interrupt is being generated at the level programmedCleared by writing a logic 1 into the Iclr control bit SCC Error Status and Interrupt Control Registers SCC Error Status RegisterSCL R Writing a 1 to this bit clears bits 25 through 28 LTOSCC Modem Interrupt Control Register AvecIRQ SCC Transmit Interrupt Control Register SCC Receive Interrupt Control Register Modem Piack Register Transmit Piack Register Receive Piack Register Lanc Error Status and Interrupt Control Registers Lanc Error Status RegisterSclr Writing a 1 to this bit clears bits 25 through 27 LTOLanc qualified by the IEN bit. When this bit is high, a 82596CA Lanc Interrupt Control RegisterInterrupt level for the 82596CA LANC. Level 0 does not This status bit reflects the state of the INT pin fromLanc Bus Error Interrupt Control Register SC0 pins, when the 82596CA Lanc performsInterrupt level. Level 0 does not generate an interrupt IL2-IL0 if nonzeroProgramming the Scsi Error Status and Interrupt Registers Scsi Error Status RegisterScsi Interrupt Control Register Interrupt level for the Scsi Processor. Level 0 does notProgramming the Printer Port Printer ACK Interrupt Control RegisterIL2-IL0 Printer Fault Interrupt Control Register FAULT. Level 0 does not generate an interruptWhen this bit is high, a printer Fault interrupt is being When this bit is high, a printer SEL interrupt is being Printer SEL Interrupt Control RegisterSEL. Level 0 does not generate an interrupt When this bit is high, a printer PE interrupt is being Printer PE Interrupt Control RegisterPE. Level 0 does not generate an interrupt When this bit is high, a printer Busy interrupt is being Printer Busy Interrupt Control RegisterBUSY. Level 0 does not generate an interrupt Printer Input Status Register Printer Port Control Register MANSTB INP DoenChip Speed Register Printer Data Register Interrupt Priority Level Register Priority Level CommentsInterrupt Mask Level Register MSK2 MSK1 MSK0PCCchip2 Computer Group Literature Center Web Site Mcecc Functions Features Mcecc functions now implemented on the Petra chip includeMcecc Functions on the Petra Asic Performance Cache Coherency Memory System Cycle TimingError Reporting Single Bit Error Cycle Type = Burst Read or Non-Burst ReadCycle Types Double Bit Error Cycle Type = Burst Read or Non-Burst Read Single Bit Error Cycle Type = Non-Burst WriteDouble Bit Error Cycle Type = Non-Burst Write Cycle Type = Burst WriteTriple or Greater Bit Error Cycle Type = Non-Burst Write Single Bit Error Cycle Type = ScrubDouble Bit Error Cycle Type = Scrub Triple or Greater Bit Error Cycle Type = ScrubError Logging ScrubRefresh Chip Defaults ArbitrationProgramming Model Mcecc Sector Internal Register Memory Map Name D31 D30 D29 D28 D27 D26 D25 D24RWB7 RWB6 1st $FFF43000/2nd $FFF43100 8-bits Memory Configuration Register MSIZ2-MSIZ0Memory Size Base Address Register Dram Control RegisterBit assignments for the Dram Control register are Bclk Frequency Register Unchanged by software or local reset Data Control RegisterMcecc Functions Scrub Control Register RWB0 RWB0 is a general-purpose read/write bitScrub Period Register Bits This register contains bits 7-0 of the Scrub Period registerChip Prescaler Counter Scrub Time On/Time Off RegisterSTOFF2-STOFF0 STON2-STON0 Scrubber Time OffScrubber Time On Scrub Prescaler Counter Bits Scrub Timer Counter Bits Scrub Address Counter Bits 1st $FFF43050/2nd $FFF43150 8-bits Error Logger Register Error Address Bits 1st $FFF43068/2nd $FFF43168 8-bits Error Syndrome Register Defaults RegisterRSIZ2-RSIZ0 SELI1, SELI0 Dram Array SizeRESST2-RESST0 Sdram Configuration Register SDCFG2-SDCFG0Initialization Programming Model Syndrome Decoding Syndrome Bit EncodingIdentifying Sdram Bank in Error ErrorMcecc Functions Computer Group Literature Center Web Site Table A-1. List of Changes Function Previous Implementation MVME1x2P2 ImplementationSummary of Changes Computer Group Literature Center Web Site Connection Diagrams Name NumberFigure B-1. MVME1X7P Printer Port with MVME712M Figure B-2. MVME1X7P Serial Port 1 Configured as DCE Figure B-3. MVME1X7P Serial Port 2 Configured as DCE Figure B-4. MVME1X7P Serial Port 3 Configured as DCE Figure B-5. MVME1X7P Serial Port 4 Configured as DCE Figure B-6. MVME1X7P Serial Port 1 Configured as DTE Figure B-7. MVME1X7P Serial Port 2 Configured as DTE Figure B-8. MVME1X7P Serial Port 3 Configured as DTE Figure B-9. MVME1X7P Serial Port 4 Configured as DTE MCG Documents Table C-1. Motorola Computer Group DocumentsDocument Title Motorola Publication Number Manufacturers’ Documents Table C-2. Manufacturers’ DocumentsDocument Title and Source Publication Number Related Specifications Table C-3. Related SpecificationsPublication Document Title and Source Number IEC 821 BUS Index Bbram 10,2-51 Gcsr IN-5 LAN IN-7 MVME1X7P IN-9 SCC Scsi IN-12 Enabling 2-32,2-35,2-43,2-44,2-50,2-51 Index