Motorola MVME1X7P manual Viii

Functional Description	1-17
VMEbus Interface and VMEchip2	1-18
VMEchip2 General-Purpose I/O	1-18
Petra/VMEchip2 Redundant Logic	1-18
Memory Maps	1-20
Local Bus Memory Map	1-20
Normal Address Range	1-20
Detailed I/O Memory Maps	1-25
BBRAM/TOD Clock Memory Map	1-41
Interrupt Acknowledge Map	1-46
VMEbus Memory Map	1-46
VMEbus Accesses to the Local Bus	1-46
VMEbus Short I/O Memory Map	1-46
Interrupt Handling	1-47
Example: VMEchip2 Tick Timer 1 Periodic Interrupt	1-47
Cache Coherency (MVME167P)	1-49
Cache Coherency (MVME177P)	1-50
Using Bus Timers	1-51
Indivisible Cycles	1-52
Supervisor Stack Pointer (MC68060)	1-53
Sources of Local Bus Errors	1-54
Local Bus Timeout	1-54
VMEbus Access Timeout	1-54
VMEbus BERR*	1-54
VMEchip2	1-55
Bus Error Processing	1-55
Error Conditions	1-55
MPU Parity Error	1-56
MPU Offboard Error	1-56
MPU TEA - Cause Unidentified	1-56
MPU Local Bus Time-out	1-57
DMAC VMEbus Error	1-57
DMAC Parity Error	1-57
DMAC Offboard Error	1-58
DMAC LTO Error	1-58
DMAC TEA - Cause Unidentified	1-59
SCC Retry Error	1-59
SCC Parity Error	1-60
SCC Offboard Error	1-60
SCC LTO Error	1-61
LAN Parity Error	1-61

viii