Motorola MVME1X7P manual List of Tables

List of Tables

Table 1-1. MVME1X7P Features Summary	1-3
Table 1-2. Functions Duplicated in VMEchip2 and Petra ASICs	1-19
Table 1-3. Local Bus Memory Map	1-21
Table 1-4. Local I/O Devices Memory Map	1-22
Table 1-5. VMEchip2 Memory Map (Sheet 1 of 3)	1-26
Table 1-6. Printer Memory Map	1-31
Table 1-7. PCCchip2 Memory Map	1-32
Table 1-8. MCECC Internal Register Memory Map	1-34
Table 1-9. Cirrus Logic CD2401 Serial Port Memory Map	1-36
Table 1-10. 82596CA Ethernet LAN Memory Map	1-40
Table 1-11. 53C710 SCSI Memory Map	1-41
Table 1-12. M48T58 BBRAM,TOD Clock Memory Map	1-42
Table 1-13. BBRAM Configuration Area Memory Map	1-42
Table 1-14. TOD Clock Memory Map	1-43
Table 1-15. Single-Cycle Instructions	1-52
Table 2-1. Features of the VMEchip2 ASIC	2-1
Table 2-2. VMEchip2 Memory Map—LCSR Summary (Sheet 1 of 2)	2-22
Table 2-3. DMAC Command Packet Format	2-53
Table 2-4. Local Bus Interrupter Summary	2-75
Table 2-5. VMEchip2 Memory Map (GCSR Summary)	2-103
Table 3-1. PCCchip2 Devices Memory Map	3-10
Table 3-2. PCCchip2 Memory Map - Control and Status Registers	3-12
Table 4-1. MCECC Functions on the Petra ASIC	4-2
Table 4-2. Memory System Cycle Timing	4-4
Table 4-3. MCECC Sector Internal Register Memory Map	4-11
Table 4-4. Syndrome Bit Encoding	4-36
Table 4-5. Identifying SDRAM Bank in Error	4-37
Table A-1. List of Changes	A-1
Table C-1. Motorola Computer Group Documents	C-1
Table C-2. Manufacturers’ Documents	C-2
Table C-3. Related Specifications	C-3

xix