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Motorola MVME1X7P manual ESW0, ESW1, ESW2, ESW3, ESW4, ESW5, ESW6, ESW7

Models: MVME1X7P

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LCSR Programming Model

Local Bus Interrupter Enable Register (bits 8-15)

ADR/SIZ			$FFF4006C (8 bits of 32)

BIT	15	14	13	12	11	10	9	8

NAME	ESW7	ESW6	ESW5	ESW4	ESW3	ESW2	ESW1	ESW0

OPER	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

RESET	0 PSL	0 PSL	0 PSL	0 PSL	0 PSL	0 PSL	0 PSL	0 PSL

This is the local bus interrupter enable register. When an enable bit is high, the corresponding interrupt is enabled. When an enable bit is low, the corresponding interrupt is disabled. The enable bit does not clear edge-sensitive interrupts or prevent the flip-flop from being set. If necessary, edge-sensitive interrupters should be cleared to remove any old interrupts and then re-enabled.

ESW0	Enable software 0 interrupt.
ESW1	Enable software 1 interrupt.
ESW2	Enable software 2 interrupt.
ESW3	Enable software 3 interrupt.
ESW4	Enable software 4 interrupt.
ESW5	Enable software 5 interrupt.
ESW6	Enable software 6 interrupt.
ESW7	Enable software 7 interrupt.

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Motorola MVME1X7P manual ESW0, ESW1, ESW2, ESW3, ESW4, ESW5, ESW6, ESW7

Contents

MVME1X7P Single-Board Computer Programmer’s Reference GuidePage Safety Summary Flammability CE Notice European Community Limited and Restricted Rights Legend Contents Viii VMEchip2 Page Page PCCchip2 Xiii Chapter Appendix a Summary of Changes Xvi List of Figures Xviii List of Tables Page About This Manual Model Number CharacteristicsComments and Suggestions Overview of ContentsConventions Used in This Manual Ctrl CR represents the carriage return or Enter keyXxv Xxvi Petra Asic and Second-Generation MVME1X7 Boards IntroductionProgramming Issues Feature FeaturesMVME1X7P Features Summary Applicable Industry Standards Block DiagramMVME167P Block Diagram MVME177P Block Diagram Data Bus Structure Programming InterfacesModel Sockets Banks EEPROMs on the MVME1X7PMVME177 Flash Memory on the MVME177Sram Onboard Sdram Interfaces Battery-Backed-Up RAM and ClockVMEbus Interface Serial Port Interface Parallel Printer Interface Ethernet Interface Scsi Interface Programmable Tick TimersLocal Resources Local Bus Timeout Watchdog TimerFunctional Description Software-Programmable Hardware InterruptsPetra/VMEchip2 Redundant Logic VMEbus Interface and VMEchip2VMEchip2 General-Purpose I/O VMEchip2 Petra Chip Address Bit # Functions Duplicated in VMEchip2 and Petra ASICsNormal Address Range Memory MapsLocal Bus Memory Map Local Bus Memory Map Local I/O Devices Memory Map Address Range Devices Accessed Port Size3KB Programming Issues Tables 1-5 through 1-14 give the detailed memory maps for Detailed I/O Memory MapsOffset VMEchip2 Memory Map Sheet 1This sheet begins on facing PRE VMEchip2 Memory Map Sheet 2Compare Register Counter Overflow Offsets Bit Numbers VMEchip2 Memory Map Sheet 3Printer Memory Map SCC Transmit Piack PCCchip2 Memory MapVector Base Register Mcecc Base Address = $FFF43000 1st $FFF43100 2nd Mcecc Internal Register Memory MapRegister Bit Names D31 D30 D29 D28 D27 D26 D25 D24Register Register Bit Names Option Registers Cirrus Logic CD2401 Serial Port Memory MapReceive Interrupt Registers Channel Command and Status RegistersInterrupt Registers Modem Interrupt Registers Transmit Interrupt RegistersDMA Registers DMA Receive RegistersDMA Transmit Registers Timer Registers10 CA Ethernet LAN Memory Map BBRAM/TOD Clock Memory Map 11 C710 Scsi Memory MapAddress Range Description Size Bytes 13. Bbram Configuration Area Memory Map12. M48T58 BBRAM,TOD Clock Memory Map Address Data Bits Function 14. TOD Clock Memory MapMVME167P-24SE 01-W3620F35C VMEbus Memory Map VMEbus Accesses to the Local BusInterrupt Acknowledge Map VMEbus Short I/O Memory MapInterrupt Handling Example VMEchip2 Tick Timer 1 Periodic InterruptTo the Tick Timer 1 Compare Register description Cache Coherency MVME167P Cache Coherency MVME177P Using Bus Timers Instructions Indivisible Cycles15. Single-Cycle Instructions Supervisor Stack Pointer MC68060 Local Bus Timeout Sources of Local Bus ErrorsVMEbus Access Timeout VMEbus BerrVMEchip2 Error ConditionsBus Error Processing MPU TEA Cause Unidentified MPU Parity ErrorMPU Offboard Error MPU Local Bus Time-out Dmac VMEbus ErrorDmac Parity Error Dmac LTO Error Dmac Offboard ErrorDmac TEA Cause Unidentified SCC Retry ErrorSCC Offboard Error SCC Parity ErrorLAN Offboard Error SCC LTO ErrorLAN Parity Error Scsi Offboard Error LAN LTO ErrorScsi Parity Error Scsi LTO Error Programming Issues Computer Group Literature Center Web Site Function Features Features of the VMEchip2 AsicVMEchip2 Introduction Local-Bus-to-VMEbus Interface Functional BlocksVMEchip2 Block Diagram VMEchip2 Local-Bus-to-VMEbus Requester VMEchip2 Functional Blocks VMEbus-to-Local-Bus InterfaceLocal-Bus-to-VMEbus DMA Controller Functional Blocks No-Address-Increment DMA Transfers Dmac VMEbus Requester Prescaler Tick and Watchdog TimersTick Timers VMEbus Interrupter VMEbus System Controller Bus TimerArbiter Iack Daisy-Chain DriverLocal Bus Interrupter and Interrupt Handler Reset DriverDmac done VMEbus Sysfail interrupterFunctional Blocks Global Control and Status Registers Lcsr Programming Model2shows a summary of the LCSRs State of the bit following a reset, defined as followsVMEchip2 Memory Map-LCSR Summary Sheet 1 IO2 IO1 VMEchip2 Memory Map-LCSR Summary Sheet 2 IRQ7 IRQ6 IRQ5 Programming the VMEbus Slave Map Decoders Lcsr Programming Model VMEbus Slave Starting Address Register VMEbus Slave Ending Address RegisterVMEbus Slave Address Translation Address Offset Register Local-bus map decoderSegment Address Translation Size Select Value VMEbus Slave Address Translation Select Register$FFF4000C 16 bits SNP2 VMEbus Slave Write Post and Snoop Control RegisterWP2 DAT VMEbus Slave Address Modifier Select RegisterPGM BLKSUP USRSNP1 WP1Block access cycles When this bit is high, the first map decoder responds toA24 access cycles CyclesVMEbus supervisory access cycles. When this bit is low A32 access cyclesProgramming the Local-Bus-to-VMEbus Map Decoders Bit is low, the first map decoder does not respond toVMEchip2 Local Bus Slave VMEbus Master Ending Address Register Local Bus Slave VMEbus Master Starting Address Register $FFF4001C 16 bits $FFF40024 16 bits Local Bus Slave VMEbus Master Attribute Register Decoder 3. Because the local-bus-to-VMEbus interface Segment defined by map decoder 3. When this bit isNot support block transfers, the block transfer address Segment defined by map decoder 2. When this bit isDecoder 2. Since the local-bus-to-VMEbus interface does Decoder 1. Because the local-bus-to-VMEbus interface Segment defined by map decoder 1. When this bit isVMEbus Slave Gcsr Group Address Register VMEbus Slave Gcsr Board Address Register EN1 Local-Bus-to-VMEbus Enable Control RegisterEN2 EN3Local-Bus-to-VMEbus I/O Control Register I2WP Programming the VMEchip2 DMA ControllerI2EN ROM Control RegisterVMEchip2 Dmac Registers Dmac Command Packet FormatEprom Decoder, Sram and DMA Control Register Entry FunctionROM0 TblscLvfair LvrwdDWB DHBDfair DrelmDtbl DENTvme Dmac Control Register 2 bitsLinc VincModified when the Dmac loads the control register from This bit is used only in command chaining mode. It is onlyControl word in the command packet. When this bit SNPDmac Local Bus Address Counter Dmac Byte Counter Dmac VMEbus Address CounterTable Address Counter Dmac VMEbus Address CounterIrql VMEbus Interrupter Control RegisterIrqs IrqcMPU Status and DMA Interrupt Count Register VMEbus Interrupter Vector RegisterDmac Status Register VMEbus Arbiter Time-Out Control Register Programming the Tick and Watchdog TimersTime on VgtoVato LbtoPrescaler register = 256- Bclock MHz Prescaler Control RegisterTick Timer 1 Counter Tick Timer 1 Compare RegisterTick timer 2 Counter Tick Timer 2 Compare RegisterTick Timer 2 Counter Board Control Register WDS/L Watchdog Timer Control RegisterWden Tick Timer 2 Control Register Prescaler Counter Tick Timer 1 Control RegisterProgramming the Local Bus Interrupter Interrupt Vector Priority for Simultaneous Interrupts Local Bus Interrupter SummaryDmac Local Bus Interrupter Status Register bits LM1 LM0SIG0 SIG1SW1 SW0SW2 SW3VME2 VME1VME3 VME4Local Bus Interrupter Enable Register bits ELM1 ELM0ESIG0 ESIG1ESW1 ESW0ESW2 ESW3EIRQ2 EIRQ1EIRQ3 EIRQ4Software Interrupt Set Register bits Interrupt Clear Register bits Interrupt Level Register 1 bits IRQ1E Level Interrupt Level Register 2 bits These bits define the level of the tick timer 1 interruptThese bits define the level of the tick timer 2 interrupt SIG3 Level SIG2 Level Interrupt Level Register 3 bits SW5 Level SW4 Level VIRQ7 Level Interrupt Level Register 4 bitsThese bits define the level of the VMEbus IRQ7 interrupt Spare LevelVIRQ3 Level Interrupts may be mapped to any local bus interrupt levelThese bits define the level of the VMEbus IRQ3 interrupt VIRQ4 LevelVBR VIRQ1 LevelVIRQ2 Level Control Register Connects to pin 17 of the Remote Status and Control Connects to pin 16 of the Remote Status and ControlConnects to pin 18 of the Remote Status and Control Not usedEnint Miscellaneous Control RegisterLcsr Programming Model Gcsr Programming Model 101 Programming the Gcsr VMEchip2 Memory Map Gcsr Summary 5shows a summary of the GcsrVMEchip2 Revision Register Offsets Bit Numbers LocaVMEchip2 LM/SIG Register VMEchip2 ID RegisterLM3 LM2RST VMEchip2 Board Status/Control RegisterISF General Purpose Register Local Bus $FFF40114/VMEbus $XXYA 16 bits PCCchip2 Summary of Major FeaturesGeneral Description PCCchip2 Block DiagramMPU Port and MPU Channel Attention Bbram Interface82596CA LAN Controller Interface MC68040-Bus Master Support for 82596CA Lanc Bus ErrorLanc Interrupt Parallel Port Interface 53C710 Scsi Controller InterfaceCD2401 SCC Interface General Purpose I/O PinPCCchip2 Tick Timer Address Range Selected Device Comments Overall Memory MapPCCchip2 Devices Memory Map Summary of the PCCchip2 CSR is shown in Table Programming ModelPCCchip2 Memory Map Control and Status Registers Fast Chip Revision Register Chip ID RegisterFast General Control RegisterDR0 Vector Base RegisterGpio IRQ Interrupt Source IV3-IV0 PriorityProgramming the Tick Timers Tick Timer 2 Compare Register Prescaler Count Register Prescaler Clock Adjust RegisterPrescaler clock adjust register = 256 Bclk MHz CEN Clear On Compare. When this bit is high, the counter isWhen this bit is low, the counter is not reset $FFF42017 8 bits Iclr General Purpose Input Interrupt Control RegisterIEN INTGeneral Purpose Input/Output Pin Control Register Tick Timer 2 Interrupt Control RegisterGPO GpoeCleared by writing a logic 1 into the Iclr control bit Interrupt Status. When this bit is high a Tick TimerInterrupt is being generated at the level programmed SCC Error Status Register SCC Error Status and Interrupt Control RegistersSCL R Writing a 1 to this bit clears bits 25 through 28 LTOIRQ SCC Modem Interrupt Control RegisterAvec SCC Transmit Interrupt Control Register SCC Receive Interrupt Control Register Modem Piack Register Transmit Piack Register Receive Piack Register Lanc Error Status Register Lanc Error Status and Interrupt Control RegistersSclr Writing a 1 to this bit clears bits 25 through 27 LTO82596CA Lanc Interrupt Control Register Lanc qualified by the IEN bit. When this bit is high, aInterrupt level for the 82596CA LANC. Level 0 does not This status bit reflects the state of the INT pin fromSC0 pins, when the 82596CA Lanc performs Lanc Bus Error Interrupt Control RegisterInterrupt level. Level 0 does not generate an interrupt IL2-IL0 if nonzeroScsi Error Status Register Programming the Scsi Error Status and Interrupt RegistersInterrupt level for the Scsi Processor. Level 0 does not Scsi Interrupt Control RegisterIL2-IL0 Programming the Printer PortPrinter ACK Interrupt Control Register When this bit is high, a printer Fault interrupt is being Printer Fault Interrupt Control RegisterFAULT. Level 0 does not generate an interrupt SEL. Level 0 does not generate an interrupt When this bit is high, a printer SEL interrupt is beingPrinter SEL Interrupt Control Register PE. Level 0 does not generate an interrupt When this bit is high, a printer PE interrupt is beingPrinter PE Interrupt Control Register BUSY. Level 0 does not generate an interrupt When this bit is high, a printer Busy interrupt is beingPrinter Busy Interrupt Control Register Printer Input Status Register STB Printer Port Control RegisterMAN Chip Speed Register INPDoen Printer Data Register Priority Level Comments Interrupt Priority Level RegisterMSK2 MSK1 MSK0 Interrupt Mask Level RegisterPCCchip2 Computer Group Literature Center Web Site Mcecc Functions Mcecc Functions on the Petra Asic FeaturesMcecc functions now implemented on the Petra chip include Performance Memory System Cycle Timing Cache CoherencyCycle Types Error ReportingSingle Bit Error Cycle Type = Burst Read or Non-Burst Read Single Bit Error Cycle Type = Non-Burst Write Double Bit Error Cycle Type = Burst Read or Non-Burst ReadDouble Bit Error Cycle Type = Non-Burst Write Cycle Type = Burst WriteSingle Bit Error Cycle Type = Scrub Triple or Greater Bit Error Cycle Type = Non-Burst WriteDouble Bit Error Cycle Type = Scrub Triple or Greater Bit Error Cycle Type = ScrubRefresh Error LoggingScrub Arbitration Chip DefaultsProgramming Model Name D31 D30 D29 D28 D27 D26 D25 D24 Mcecc Sector Internal Register Memory MapRWB7 RWB6 1st $FFF43000/2nd $FFF43100 8-bits Memory Size Memory Configuration RegisterMSIZ2-MSIZ0 Bit assignments for the Dram Control register are Base Address RegisterDram Control Register Bclk Frequency Register Data Control Register Unchanged by software or local resetMcecc Functions RWB0 RWB0 is a general-purpose read/write bit Scrub Control RegisterThis register contains bits 7-0 of the Scrub Period register Scrub Period Register BitsSTOFF2-STOFF0 Chip Prescaler CounterScrub Time On/Time Off Register Scrubber Time On STON2-STON0Scrubber Time Off Scrub Prescaler Counter Bits Scrub Timer Counter Bits Scrub Address Counter Bits 1st $FFF43050/2nd $FFF43150 8-bits Error Logger Register Error Address Bits 1st $FFF43068/2nd $FFF43168 8-bits RSIZ2-RSIZ0 Error Syndrome RegisterDefaults Register Dram Array Size SELI1, SELI0RESST2-RESST0 SDCFG2-SDCFG0 Sdram Configuration RegisterInitialization Programming Model Syndrome Bit Encoding Syndrome DecodingError Identifying Sdram Bank in ErrorMcecc Functions Computer Group Literature Center Web Site Function Previous Implementation MVME1x2P2 Implementation Table A-1. List of ChangesSummary of Changes Computer Group Literature Center Web Site Name Number Connection DiagramsFigure B-1. MVME1X7P Printer Port with MVME712M Figure B-2. MVME1X7P Serial Port 1 Configured as DCE Figure B-3. MVME1X7P Serial Port 2 Configured as DCE Figure B-4. MVME1X7P Serial Port 3 Configured as DCE Figure B-5. MVME1X7P Serial Port 4 Configured as DCE Figure B-6. MVME1X7P Serial Port 1 Configured as DTE Figure B-7. MVME1X7P Serial Port 2 Configured as DTE Figure B-8. MVME1X7P Serial Port 3 Configured as DTE Figure B-9. MVME1X7P Serial Port 4 Configured as DTE Document Title Motorola Publication Number MCG DocumentsTable C-1. Motorola Computer Group Documents Document Title and Source Publication Number Manufacturers’ DocumentsTable C-2. Manufacturers’ Documents Publication Document Title and Source Number Related SpecificationsTable C-3. Related Specifications IEC 821 BUS Index Bbram 10,2-51 Gcsr IN-5 LAN IN-7 MVME1X7P IN-9 SCC Scsi IN-12 Enabling 2-32,2-35,2-43,2-44,2-50,2-51 Index