Motorola MVME1X7P manual Bclk Frequency Register

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MCECC Functions

NCEBEN Setting the NCEBEN control bit enables the MCECC pair to assert TEA∗ when a non-correctable error occurs during a local bus access to memory. In some cases setting NCEBEN causes DRAM accesses to be delayed by one clock. This delay is incurred when the access is a local bus (or scrub) read and the FSTRD bit is set.

NCEIEN When NCEIEN is set, the logging of a non-correctable error causes the INT signal pin to pulse true. Note that NCEIEN has no effect on DRAM access time.

RWB3 Read/Write Bit 3 is a general purpose read/write bit.

RWB4 Read/Write Bit 4 is a general purpose read/write bit.

RWB5 Read/Write Bit 5 is a general purpose read/write bit.

BAD22, BAD23

These are the lower two bits of the DRAM base address described in the previous register.

BCLK Frequency Register

The Bus Clock (BCLK) Frequency register should be programmed with the hexadecimal value of the operating clock frequency in MHz (i.e., $19 for 25MHz and $21 for 33MHz). The MCECC sector pair uses the value programmed in this register to control the Prescaler counter. The Prescaler counter increments to $FF and then it is loaded with the two’s complement of the value in the BCLK Frequency register. This produces a 1MHz clock that is used by the refresh timer and the scrubber. When the BCLK Frequency register is correctly programmed with the BCLK frequency, the DRAMs are refreshed approximately once every 15.6 microseconds. After power-up, this register is initialized to $19 (for 25MHz).

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