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Motorola MVME1X7P manual SELI1, SELI0, Dram Array Size

Models: MVME1X7P

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Programming Model

RSIZ2	RSIZ1	RSIZ0	DRAM Array Size

0	0	0	4MB

0	0	1	8MB

0	1	0	16MB

0	1	1	32MB

1	0	0	64MB

1	0	1	128MB

1	1	0	Reserved

1	1	1	Reserved

The states of RSIZ2-0 after reset (power-up, soft, or local) match those of the RSIZ2-0 bits from the reset serial bit stream.

SELI1, SELI0

The SELI1, SELI0 control bits determine the base address at which the control and status registers respond, as shown below:

SELI1	SELI0	Register Base Address

0	1	$FFF43000

1	0	$FFF43100

SELI1 and SELI0 are initialized by hardware after a power-up, soft, or local reset. Their initialized state is determined by board-level configuration resistors.

FSTRD The FSTRD control bit determines the speed at which SDRAM reads occur. When it is 1, SDRAM reads happen at full speed. When it is 0, SDRAM reads are slowed by one clock, unless they are already slowed by NCEBEN

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Motorola MVME1X7P manual SELI1, SELI0, Dram Array Size

Contents

MVME1X7P Single-Board Computer Programmer’s Reference GuidePage Safety Summary Flammability CE Notice European Community Limited and Restricted Rights Legend Contents Viii VMEchip2 Page Page PCCchip2 Xiii Chapter Appendix a Summary of Changes Xvi List of Figures Xviii List of Tables Page About This Manual Model Number CharacteristicsComments and Suggestions Overview of ContentsConventions Used in This Manual Ctrl CR represents the carriage return or Enter keyXxv Xxvi Petra Asic and Second-Generation MVME1X7 Boards IntroductionProgramming Issues Features MVME1X7P Features SummaryFeature Applicable Industry Standards Block DiagramMVME167P Block Diagram MVME177P Block Diagram Data Bus Structure Programming InterfacesModel Sockets Banks EEPROMs on the MVME1X7PMVME177 Flash Memory on the MVME177Sram Onboard Sdram Battery-Backed-Up RAM and Clock VMEbus InterfaceInterfaces Serial Port Interface Parallel Printer Interface Ethernet Interface Programmable Tick Timers Local ResourcesScsi Interface Software-Programmable Hardware Interrupts Watchdog TimerLocal Bus Timeout Functional DescriptionVMEbus Interface and VMEchip2 VMEchip2 General-Purpose I/OPetra/VMEchip2 Redundant Logic VMEchip2 Petra Chip Address Bit # Functions Duplicated in VMEchip2 and Petra ASICsMemory Maps Local Bus Memory MapNormal Address Range Local Bus Memory Map Local I/O Devices Memory Map Address Range Devices Accessed Port Size3KB Programming Issues Tables 1-5 through 1-14 give the detailed memory maps for Detailed I/O Memory MapsOffset VMEchip2 Memory Map Sheet 1This sheet begins on facing PRE VMEchip2 Memory Map Sheet 2Compare Register Counter Overflow Offsets Bit Numbers VMEchip2 Memory Map Sheet 3Printer Memory Map SCC Transmit Piack PCCchip2 Memory MapVector Base Register D31 D30 D29 D28 D27 D26 D25 D24 Mcecc Internal Register Memory MapMcecc Base Address = $FFF43000 1st $FFF43100 2nd Register Bit NamesRegister Register Bit Names Option Registers Cirrus Logic CD2401 Serial Port Memory MapChannel Command and Status Registers Interrupt RegistersReceive Interrupt Registers DMA Receive Registers Transmit Interrupt RegistersModem Interrupt Registers DMA RegistersDMA Transmit Registers Timer Registers10 CA Ethernet LAN Memory Map BBRAM/TOD Clock Memory Map 11 C710 Scsi Memory Map13. Bbram Configuration Area Memory Map 12. M48T58 BBRAM,TOD Clock Memory MapAddress Range Description Size Bytes Address Data Bits Function 14. TOD Clock Memory MapMVME167P-24SE 01-W3620F35C VMEbus Short I/O Memory Map VMEbus Accesses to the Local BusVMEbus Memory Map Interrupt Acknowledge MapInterrupt Handling Example VMEchip2 Tick Timer 1 Periodic InterruptTo the Tick Timer 1 Compare Register description Cache Coherency MVME167P Cache Coherency MVME177P Using Bus Timers Indivisible Cycles 15. Single-Cycle InstructionsInstructions Supervisor Stack Pointer MC68060 VMEbus Berr Sources of Local Bus ErrorsLocal Bus Timeout VMEbus Access TimeoutError Conditions Bus Error ProcessingVMEchip2 MPU Parity Error MPU Offboard ErrorMPU TEA Cause Unidentified Dmac VMEbus Error Dmac Parity ErrorMPU Local Bus Time-out Dmac LTO Error Dmac Offboard ErrorDmac TEA Cause Unidentified SCC Retry ErrorSCC Offboard Error SCC Parity ErrorSCC LTO Error LAN Parity ErrorLAN Offboard Error LAN LTO Error Scsi Parity ErrorScsi Offboard Error Scsi LTO Error Programming Issues Computer Group Literature Center Web Site Function Features Features of the VMEchip2 AsicVMEchip2 Introduction Local-Bus-to-VMEbus Interface Functional BlocksVMEchip2 Block Diagram VMEchip2 Local-Bus-to-VMEbus Requester VMEchip2 Functional Blocks VMEbus-to-Local-Bus InterfaceLocal-Bus-to-VMEbus DMA Controller Functional Blocks No-Address-Increment DMA Transfers Dmac VMEbus Requester Prescaler Tick and Watchdog TimersTick Timers VMEbus Interrupter Iack Daisy-Chain Driver Bus TimerVMEbus System Controller ArbiterVMEbus Sysfail interrupter Reset DriverLocal Bus Interrupter and Interrupt Handler Dmac doneFunctional Blocks Global Control and Status Registers Lcsr Programming Model2shows a summary of the LCSRs State of the bit following a reset, defined as followsVMEchip2 Memory Map-LCSR Summary Sheet 1 IO2 IO1 VMEchip2 Memory Map-LCSR Summary Sheet 2 IRQ7 IRQ6 IRQ5 Programming the VMEbus Slave Map Decoders Lcsr Programming Model VMEbus Slave Starting Address Register VMEbus Slave Ending Address RegisterVMEbus Slave Address Translation Address Offset Register Local-bus map decoderSegment Address Translation Size Select Value VMEbus Slave Address Translation Select Register$FFF4000C 16 bits VMEbus Slave Write Post and Snoop Control Register WP2SNP2 BLK VMEbus Slave Address Modifier Select RegisterDAT PGMSUP USRSNP1 WP1Cycles When this bit is high, the first map decoder responds toBlock access cycles A24 access cyclesBit is low, the first map decoder does not respond to A32 access cyclesVMEbus supervisory access cycles. When this bit is low Programming the Local-Bus-to-VMEbus Map DecodersVMEchip2 Local Bus Slave VMEbus Master Ending Address Register Local Bus Slave VMEbus Master Starting Address Register $FFF4001C 16 bits $FFF40024 16 bits Local Bus Slave VMEbus Master Attribute Register Decoder 3. Because the local-bus-to-VMEbus interface Segment defined by map decoder 3. When this bit isSegment defined by map decoder 2. When this bit is Decoder 2. Since the local-bus-to-VMEbus interface doesNot support block transfers, the block transfer address Decoder 1. Because the local-bus-to-VMEbus interface Segment defined by map decoder 1. When this bit isVMEbus Slave Gcsr Group Address Register VMEbus Slave Gcsr Board Address Register EN3 Local-Bus-to-VMEbus Enable Control RegisterEN1 EN2Local-Bus-to-VMEbus I/O Control Register ROM Control Register Programming the VMEchip2 DMA ControllerI2WP I2ENVMEchip2 Entry Function Dmac Command Packet FormatDmac Registers Eprom Decoder, Sram and DMA Control RegisterROM0 TblscDHB LvrwdLvfair DWBDEN DrelmDfair DtblVinc Dmac Control Register 2 bitsTvme LincSNP This bit is used only in command chaining mode. It is onlyModified when the Dmac loads the control register from Control word in the command packet. When this bitDmac Local Bus Address Counter Dmac VMEbus Address Counter Dmac VMEbus Address CounterDmac Byte Counter Table Address CounterIrqc VMEbus Interrupter Control RegisterIrql IrqsMPU Status and DMA Interrupt Count Register VMEbus Interrupter Vector RegisterDmac Status Register VMEbus Arbiter Time-Out Control Register Programming the Tick and Watchdog TimersTime on VgtoVato LbtoPrescaler register = 256- Bclock MHz Prescaler Control RegisterTick Timer 1 Counter Tick Timer 1 Compare RegisterTick Timer 2 Compare Register Tick Timer 2 CounterTick timer 2 Counter Board Control Register Watchdog Timer Control Register WdenWDS/L Tick Timer 2 Control Register Prescaler Counter Tick Timer 1 Control RegisterProgramming the Local Bus Interrupter Interrupt Vector Priority for Simultaneous Interrupts Local Bus Interrupter SummaryDmac Local Bus Interrupter Status Register bits SIG1 LM0LM1 SIG0SW3 SW0SW1 SW2VME4 VME1VME2 VME3Local Bus Interrupter Enable Register bits ESIG1 ELM0ELM1 ESIG0ESW3 ESW0ESW1 ESW2EIRQ4 EIRQ1EIRQ2 EIRQ3Software Interrupt Set Register bits Interrupt Clear Register bits Interrupt Level Register 1 bits IRQ1E Level These bits define the level of the tick timer 1 interrupt These bits define the level of the tick timer 2 interruptInterrupt Level Register 2 bits SIG3 Level SIG2 Level Interrupt Level Register 3 bits SW5 Level SW4 Level Spare Level Interrupt Level Register 4 bitsVIRQ7 Level These bits define the level of the VMEbus IRQ7 interruptVIRQ4 Level Interrupts may be mapped to any local bus interrupt levelVIRQ3 Level These bits define the level of the VMEbus IRQ3 interruptVIRQ1 Level VIRQ2 LevelVBR Control Register Not used Connects to pin 16 of the Remote Status and ControlConnects to pin 17 of the Remote Status and Control Connects to pin 18 of the Remote Status and ControlEnint Miscellaneous Control RegisterLcsr Programming Model Gcsr Programming Model 101 Programming the Gcsr Offsets Bit Numbers Loca 5shows a summary of the GcsrVMEchip2 Memory Map Gcsr Summary VMEchip2 Revision RegisterVMEchip2 LM/SIG Register VMEchip2 ID RegisterLM3 LM2VMEchip2 Board Status/Control Register ISFRST General Purpose Register Local Bus $FFF40114/VMEbus $XXYA 16 bits PCCchip2 Summary of Major FeaturesGeneral Description PCCchip2 Block DiagramBbram Interface 82596CA LAN Controller InterfaceMPU Port and MPU Channel Attention MC68040-Bus Master Support for 82596CA Lanc Bus ErrorLanc Interrupt Parallel Port Interface 53C710 Scsi Controller InterfaceCD2401 SCC Interface General Purpose I/O PinPCCchip2 Tick Timer Overall Memory Map PCCchip2 Devices Memory MapAddress Range Selected Device Comments Summary of the PCCchip2 CSR is shown in Table Programming ModelPCCchip2 Memory Map Control and Status Registers Fast Chip Revision Register Chip ID RegisterFast General Control RegisterDR0 Vector Base RegisterGpio IRQ Interrupt Source IV3-IV0 PriorityProgramming the Tick Timers Tick Timer 2 Compare Register Prescaler Count Register Prescaler Clock Adjust RegisterPrescaler clock adjust register = 256 Bclk MHz Clear On Compare. When this bit is high, the counter is When this bit is low, the counter is not resetCEN $FFF42017 8 bits INT General Purpose Input Interrupt Control RegisterIclr IENGpoe Tick Timer 2 Interrupt Control RegisterGeneral Purpose Input/Output Pin Control Register GPOInterrupt Status. When this bit is high a Tick Timer Interrupt is being generated at the level programmedCleared by writing a logic 1 into the Iclr control bit Writing a 1 to this bit clears bits 25 through 28 LTO SCC Error Status and Interrupt Control RegistersSCC Error Status Register SCL RSCC Modem Interrupt Control Register AvecIRQ SCC Transmit Interrupt Control Register SCC Receive Interrupt Control Register Modem Piack Register Transmit Piack Register Receive Piack Register Writing a 1 to this bit clears bits 25 through 27 LTO Lanc Error Status and Interrupt Control RegistersLanc Error Status Register SclrThis status bit reflects the state of the INT pin from Lanc qualified by the IEN bit. When this bit is high, a82596CA Lanc Interrupt Control Register Interrupt level for the 82596CA LANC. Level 0 does notIL2-IL0 if nonzero Lanc Bus Error Interrupt Control RegisterSC0 pins, when the 82596CA Lanc performs Interrupt level. Level 0 does not generate an interruptScsi Error Status Register Programming the Scsi Error Status and Interrupt RegistersInterrupt level for the Scsi Processor. Level 0 does not Scsi Interrupt Control RegisterProgramming the Printer Port Printer ACK Interrupt Control RegisterIL2-IL0 Printer Fault Interrupt Control Register FAULT. Level 0 does not generate an interruptWhen this bit is high, a printer Fault interrupt is being When this bit is high, a printer SEL interrupt is being Printer SEL Interrupt Control RegisterSEL. Level 0 does not generate an interrupt When this bit is high, a printer PE interrupt is being Printer PE Interrupt Control RegisterPE. Level 0 does not generate an interrupt When this bit is high, a printer Busy interrupt is being Printer Busy Interrupt Control RegisterBUSY. Level 0 does not generate an interrupt Printer Input Status Register Printer Port Control Register MANSTB INP DoenChip Speed Register Printer Data Register Priority Level Comments Interrupt Priority Level RegisterMSK2 MSK1 MSK0 Interrupt Mask Level RegisterPCCchip2 Computer Group Literature Center Web Site Mcecc Functions Features Mcecc functions now implemented on the Petra chip includeMcecc Functions on the Petra Asic Performance Memory System Cycle Timing Cache CoherencyError Reporting Single Bit Error Cycle Type = Burst Read or Non-Burst ReadCycle Types Cycle Type = Burst Write Double Bit Error Cycle Type = Burst Read or Non-Burst ReadSingle Bit Error Cycle Type = Non-Burst Write Double Bit Error Cycle Type = Non-Burst WriteTriple or Greater Bit Error Cycle Type = Scrub Triple or Greater Bit Error Cycle Type = Non-Burst WriteSingle Bit Error Cycle Type = Scrub Double Bit Error Cycle Type = ScrubError Logging ScrubRefresh Arbitration Chip DefaultsProgramming Model Name D31 D30 D29 D28 D27 D26 D25 D24 Mcecc Sector Internal Register Memory MapRWB7 RWB6 1st $FFF43000/2nd $FFF43100 8-bits Memory Configuration Register MSIZ2-MSIZ0Memory Size Base Address Register Dram Control RegisterBit assignments for the Dram Control register are Bclk Frequency Register Data Control Register Unchanged by software or local resetMcecc Functions RWB0 RWB0 is a general-purpose read/write bit Scrub Control RegisterThis register contains bits 7-0 of the Scrub Period register Scrub Period Register BitsChip Prescaler Counter Scrub Time On/Time Off RegisterSTOFF2-STOFF0 STON2-STON0 Scrubber Time OffScrubber Time On Scrub Prescaler Counter Bits Scrub Timer Counter Bits Scrub Address Counter Bits 1st $FFF43050/2nd $FFF43150 8-bits Error Logger Register Error Address Bits 1st $FFF43068/2nd $FFF43168 8-bits Error Syndrome Register Defaults RegisterRSIZ2-RSIZ0 Dram Array Size SELI1, SELI0RESST2-RESST0 SDCFG2-SDCFG0 Sdram Configuration RegisterInitialization Programming Model Syndrome Bit Encoding Syndrome DecodingError Identifying Sdram Bank in ErrorMcecc Functions Computer Group Literature Center Web Site Function Previous Implementation MVME1x2P2 Implementation Table A-1. List of ChangesSummary of Changes Computer Group Literature Center Web Site Name Number Connection DiagramsFigure B-1. MVME1X7P Printer Port with MVME712M Figure B-2. MVME1X7P Serial Port 1 Configured as DCE Figure B-3. MVME1X7P Serial Port 2 Configured as DCE Figure B-4. MVME1X7P Serial Port 3 Configured as DCE Figure B-5. MVME1X7P Serial Port 4 Configured as DCE Figure B-6. MVME1X7P Serial Port 1 Configured as DTE Figure B-7. MVME1X7P Serial Port 2 Configured as DTE Figure B-8. MVME1X7P Serial Port 3 Configured as DTE Figure B-9. MVME1X7P Serial Port 4 Configured as DTE MCG Documents Table C-1. Motorola Computer Group DocumentsDocument Title Motorola Publication Number Manufacturers’ Documents Table C-2. Manufacturers’ DocumentsDocument Title and Source Publication Number Related Specifications Table C-3. Related SpecificationsPublication Document Title and Source Number IEC 821 BUS Index Bbram 10,2-51 Gcsr IN-5 LAN IN-7 MVME1X7P IN-9 SCC Scsi IN-12 Enabling 2-32,2-35,2-43,2-44,2-50,2-51 Index