3

PCCchip2

SCSI Interrupt Control Register

ADR/SIZ

 

 

 

 

$FFF4202F (8 bits)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

7

6

 

5

 

4

 

3

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

NAME

 

 

 

IRQ

 

IEN

 

 

 

IL2

IL1

IL0

 

 

 

 

 

 

 

 

 

 

 

 

 

OPER

R/W

R/W

 

R

 

R/W

 

R/W

 

R/W

R/W

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET

0 PL

0 PL

 

0 PL

 

0 PL

 

0 PL

 

0 PL

0 PL

0 PL

 

 

 

 

 

 

 

 

 

 

 

IL2-IL0

 

Interrupt Request Level. These three bits select the

 

 

 

interrupt level for the SCSI Processor. Level 0 does not

 

 

 

generate an interrupt.

 

 

 

 

 

 

IEN

 

Interrupt Enable. When this bit is high, the interrupt is

 

 

 

enabled. The interrupt is disabled when this bit is low.

 

IRQ

 

Interrupt Status. This status bit reflects the state of the

 

 

 

IRQ* pin of the SCSI Processor (qualified by the IEN bit).

When this bit is high, a SCSI processor interrupt is being generated at the level programmed in IL2-IL0 (if nonzero). This status bit does not need to be cleared, because it is not edge-sensitive.

3-38

Computer Group Literature Center Web Site

Page 236
Image 236
Motorola MVME1X7P manual Scsi Interrupt Control Register, Interrupt level for the Scsi Processor. Level 0 does not