Motorola MVME1X7P manual General Control Register, Fast

Programming Model

General Control Register

The General Control Register is located at $FFF42002. It is an 8-bit register that controls chip general functions. The Master Interrupt Enable bit (MIEN) must be set high for any interrupts from the PCCchip2 to be asserted to the processor.

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ADR/SIZ					$FFF42002 (8 bits)
DIR	15	14		13		12	11	10	9	8
NAME	DR0							C040	MIEN	FAST
OPER	R/W	R		R		R	R	R/W	R/W	R/W
RESET	V PL	0		0		0	0	0 P	0 PL	0 P
	FAST		This control bit tailors the control circuit for BBRAM to
			the speed of BBRAM.
	Note The PCCchip2 runs at half the MPU speed on the MVME177P.
		For example, an MVME177P with a 50 MHz MPU will run the
		PCCchip2 at 25 MHz.
			When operating at 25 MHz, the FAST bit should be
			cleared for devices with access times longer than 200 ns
			(5 CLK cycles). The bit can be set for devices that have
			access times of 200 ns or faster. It is not allowed to use
			devices slower than 360 ns (9 CLK cycles), at 25 MHz.
			When operating at 33 MHz, the FAST bit should be
			cleared for devices with access times longer than 150 ns
			(5 CLK cycles). The bit can be set for devices that have
			access times 150 ns or faster. It is not allowed to use
			devices slower than 270 ns (9 CLK cycles), at 33 MHz.
	MIEN		Master Interrupt Enable. When this bit is high, interrupts
			from and via the PCCchip2 are allowed to reach the MPU.
			When it is low, all interrupts from the PCCchip2 are
			disabled (this includes both the EIPL* pins and the INT
			pin). Also, when the bit is low, all interrupt acknowledge

cycles to the PCCchip2 are passed on, via the IACKOUT* pin. This bit is cleared by a reset.

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