Functional Description, Performance | Motorola MVME1X7P instruction

Functional Description

Functional Description

The following sections provide an overview of the functions provided by the Petra MCECC sector. For a detailed programming model for the Petra/MCECC control and status registers, refer to the Programming Model section.

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General Description

The Petra MCECC sector is a single-chip solution for memory control functions. The memory architecture is a single bank of SDRAM, 32 bits wide plus seven check bits. The MCECC sector provides all the functions required to implement a memory system. These include programmable map decoding, memory control, refresh, and a memory scrubber. The scrubber, when enabled, periodically scans memory for errors. If the scrubber finds a single-bit error in the memory array, it corrects the error. This prevents soft single-bit errors from becoming double-bit errors.

Performance

The Petra MCECC sector maintains tags for each internal bank of SDRAM. Each bank may be in an active or idle state. SDRAM access time is a function of the state of the bank of memory being addressed. If the bank addressed is active, performance is additionally a function of the page of memory being referenced. If the page referenced is open, access time is the shortest possible. Maximum access time will occur when the page referenced is not open, since the open page must be first closed and the desired page then opened.

Page sizes are determined by the configuration of the SDRAM device. Sizes range from 256 to 1024 memory locations per page.

The Petra MCECC sector design is targeted for SDRAM devices of the PC100 type. Memory access time are not influenced by the settings of mode bits or SDRAM speed selections.

The basic performance specifications for the MCECC sector are listed in Table 4-2.

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Motorola MVME1X7P manual Functional Description, Performance

Contents

MVME1X7P Single-Board Computer Programmer’s Reference GuidePage Safety Summary Flammability CE Notice European Community Limited and Restricted Rights Legend Contents Viii VMEchip2 Page Page PCCchip2 Xiii Chapter Appendix a Summary of Changes Xvi List of Figures Xviii List of Tables Page About This Manual Model Number Characteristics Comments and Suggestions Overview of Contents Conventions Used in This Manual Ctrl CR represents the carriage return or Enter key Xxv Xxvi Petra Asic and Second-Generation MVME1X7 Boards Introduction Programming Issues Feature FeaturesMVME1X7P Features Summary Applicable Industry Standards Block Diagram MVME167P Block Diagram MVME177P Block Diagram Data Bus Structure Programming Interfaces Model Sockets Banks EEPROMs on the MVME1X7P MVME177 Flash Memory on the MVME177 Sram Onboard Sdram Interfaces Battery-Backed-Up RAM and ClockVMEbus Interface Serial Port Interface Parallel Printer Interface Ethernet Interface Scsi Interface Programmable Tick TimersLocal Resources Software-Programmable Hardware Interrupts Watchdog TimerLocal Bus Timeout Functional Description Petra/VMEchip2 Redundant Logic VMEbus Interface and VMEchip2VMEchip2 General-Purpose I/O VMEchip2 Petra Chip Address Bit # Functions Duplicated in VMEchip2 and Petra ASICs Normal Address Range Memory MapsLocal Bus Memory Map Local Bus Memory Map Local I/O Devices Memory Map Address Range Devices Accessed Port Size 3KB Programming Issues Tables 1-5 through 1-14 give the detailed memory maps for Detailed I/O Memory Maps Offset VMEchip2 Memory Map Sheet 1 This sheet begins on facing PRE VMEchip2 Memory Map Sheet 2 Compare Register Counter Overflow Offsets Bit Numbers VMEchip2 Memory Map Sheet 3 Printer Memory Map SCC Transmit Piack PCCchip2 Memory Map Vector Base Register D31 D30 D29 D28 D27 D26 D25 D24 Mcecc Internal Register Memory MapMcecc Base Address = $FFF43000 1st $FFF43100 2nd Register Bit Names Register Register Bit Names Option Registers Cirrus Logic CD2401 Serial Port Memory Map Receive Interrupt Registers Channel Command and Status RegistersInterrupt Registers DMA Receive Registers Transmit Interrupt RegistersModem Interrupt Registers DMA Registers DMA Transmit Registers Timer Registers 10 CA Ethernet LAN Memory Map BBRAM/TOD Clock Memory Map 11 C710 Scsi Memory Map Address Range Description Size Bytes 13. Bbram Configuration Area Memory Map12. M48T58 BBRAM,TOD Clock Memory Map Address Data Bits Function 14. TOD Clock Memory Map MVME167P-24SE 01-W3620F35C VMEbus Short I/O Memory Map VMEbus Accesses to the Local BusVMEbus Memory Map Interrupt Acknowledge Map Interrupt Handling Example VMEchip2 Tick Timer 1 Periodic Interrupt To the Tick Timer 1 Compare Register description Cache Coherency MVME167P Cache Coherency MVME177P Using Bus Timers Instructions Indivisible Cycles15. Single-Cycle Instructions Supervisor Stack Pointer MC68060 VMEbus Berr Sources of Local Bus ErrorsLocal Bus Timeout VMEbus Access Timeout VMEchip2 Error ConditionsBus Error Processing MPU TEA Cause Unidentified MPU Parity ErrorMPU Offboard Error MPU Local Bus Time-out Dmac VMEbus ErrorDmac Parity Error Dmac LTO Error Dmac Offboard Error Dmac TEA Cause Unidentified SCC Retry Error SCC Offboard Error SCC Parity Error LAN Offboard Error SCC LTO ErrorLAN Parity Error Scsi Offboard Error LAN LTO ErrorScsi Parity Error Scsi LTO Error Programming Issues Computer Group Literature Center Web Site Function Features Features of the VMEchip2 Asic VMEchip2 Introduction Local-Bus-to-VMEbus Interface Functional Blocks VMEchip2 Block Diagram VMEchip2 Local-Bus-to-VMEbus Requester VMEchip2 Functional Blocks VMEbus-to-Local-Bus Interface Local-Bus-to-VMEbus DMA Controller Functional Blocks No-Address-Increment DMA Transfers Dmac VMEbus Requester Prescaler Tick and Watchdog Timers Tick Timers VMEbus Interrupter Iack Daisy-Chain Driver Bus TimerVMEbus System Controller Arbiter VMEbus Sysfail interrupter Reset DriverLocal Bus Interrupter and Interrupt Handler Dmac done Functional Blocks Global Control and Status Registers Lcsr Programming Model 2shows a summary of the LCSRs State of the bit following a reset, defined as follows VMEchip2 Memory Map-LCSR Summary Sheet 1 IO2 IO1 VMEchip2 Memory Map-LCSR Summary Sheet 2 IRQ7 IRQ6 IRQ5 Programming the VMEbus Slave Map Decoders Lcsr Programming Model VMEbus Slave Starting Address Register VMEbus Slave Ending Address Register VMEbus Slave Address Translation Address Offset Register Local-bus map decoder Segment Address Translation Size Select Value VMEbus Slave Address Translation Select Register $FFF4000C 16 bits SNP2 VMEbus Slave Write Post and Snoop Control RegisterWP2 BLK VMEbus Slave Address Modifier Select RegisterDAT PGM SUP USR SNP1 WP1 Cycles When this bit is high, the first map decoder responds toBlock access cycles A24 access cycles Bit is low, the first map decoder does not respond to A32 access cyclesVMEbus supervisory access cycles. When this bit is low Programming the Local-Bus-to-VMEbus Map Decoders VMEchip2 Local Bus Slave VMEbus Master Ending Address Register Local Bus Slave VMEbus Master Starting Address Register $FFF4001C 16 bits $FFF40024 16 bits Local Bus Slave VMEbus Master Attribute Register Decoder 3. Because the local-bus-to-VMEbus interface Segment defined by map decoder 3. When this bit is Not support block transfers, the block transfer address Segment defined by map decoder 2. When this bit isDecoder 2. Since the local-bus-to-VMEbus interface does Decoder 1. Because the local-bus-to-VMEbus interface Segment defined by map decoder 1. When this bit is VMEbus Slave Gcsr Group Address Register VMEbus Slave Gcsr Board Address Register EN3 Local-Bus-to-VMEbus Enable Control RegisterEN1 EN2 Local-Bus-to-VMEbus I/O Control Register ROM Control Register Programming the VMEchip2 DMA ControllerI2WP I2EN VMEchip2 Entry Function Dmac Command Packet FormatDmac Registers Eprom Decoder, Sram and DMA Control Register ROM0 Tblsc DHB LvrwdLvfair DWB DEN DrelmDfair Dtbl Vinc Dmac Control Register 2 bitsTvme Linc SNP This bit is used only in command chaining mode. It is onlyModified when the Dmac loads the control register from Control word in the command packet. When this bit Dmac Local Bus Address Counter Dmac VMEbus Address Counter Dmac VMEbus Address CounterDmac Byte Counter Table Address Counter Irqc VMEbus Interrupter Control RegisterIrql Irqs MPU Status and DMA Interrupt Count Register VMEbus Interrupter Vector Register Dmac Status Register VMEbus Arbiter Time-Out Control Register Programming the Tick and Watchdog Timers Time on Vgto Vato Lbto Prescaler register = 256- Bclock MHz Prescaler Control Register Tick Timer 1 Counter Tick Timer 1 Compare Register Tick timer 2 Counter Tick Timer 2 Compare RegisterTick Timer 2 Counter Board Control Register WDS/L Watchdog Timer Control RegisterWden Tick Timer 2 Control Register Prescaler Counter Tick Timer 1 Control Register Programming the Local Bus Interrupter Interrupt Vector Priority for Simultaneous Interrupts Local Bus Interrupter Summary Dmac Local Bus Interrupter Status Register bits SIG1 LM0LM1 SIG0 SW3 SW0SW1 SW2 VME4 VME1VME2 VME3 Local Bus Interrupter Enable Register bits ESIG1 ELM0ELM1 ESIG0 ESW3 ESW0ESW1 ESW2 EIRQ4 EIRQ1EIRQ2 EIRQ3 Software Interrupt Set Register bits Interrupt Clear Register bits Interrupt Level Register 1 bits IRQ1E Level Interrupt Level Register 2 bits These bits define the level of the tick timer 1 interruptThese bits define the level of the tick timer 2 interrupt SIG3 Level SIG2 Level Interrupt Level Register 3 bits SW5 Level SW4 Level Spare Level Interrupt Level Register 4 bitsVIRQ7 Level These bits define the level of the VMEbus IRQ7 interrupt VIRQ4 Level Interrupts may be mapped to any local bus interrupt levelVIRQ3 Level These bits define the level of the VMEbus IRQ3 interrupt VBR VIRQ1 LevelVIRQ2 Level Control Register Not used Connects to pin 16 of the Remote Status and ControlConnects to pin 17 of the Remote Status and Control Connects to pin 18 of the Remote Status and Control Enint Miscellaneous Control Register Lcsr Programming Model Gcsr Programming Model 101 Programming the Gcsr Offsets Bit Numbers Loca 5shows a summary of the GcsrVMEchip2 Memory Map Gcsr Summary VMEchip2 Revision Register VMEchip2 LM/SIG Register VMEchip2 ID Register LM3 LM2 RST VMEchip2 Board Status/Control RegisterISF General Purpose Register Local Bus $FFF40114/VMEbus $XXYA 16 bits PCCchip2 Summary of Major Features General Description PCCchip2 Block Diagram MPU Port and MPU Channel Attention Bbram Interface82596CA LAN Controller Interface MC68040-Bus Master Support for 82596CA Lanc Bus Error Lanc Interrupt Parallel Port Interface 53C710 Scsi Controller Interface CD2401 SCC Interface General Purpose I/O Pin PCCchip2 Tick Timer Address Range Selected Device Comments Overall Memory MapPCCchip2 Devices Memory Map Summary of the PCCchip2 CSR is shown in Table Programming Model PCCchip2 Memory Map Control and Status Registers Fast Chip Revision Register Chip ID Register Fast General Control Register DR0 Vector Base Register Gpio IRQ Interrupt Source IV3-IV0 Priority Programming the Tick Timers Tick Timer 2 Compare Register Prescaler Count Register Prescaler Clock Adjust Register Prescaler clock adjust register = 256 Bclk MHz CEN Clear On Compare. When this bit is high, the counter isWhen this bit is low, the counter is not reset $FFF42017 8 bits INT General Purpose Input Interrupt Control RegisterIclr IEN Gpoe Tick Timer 2 Interrupt Control RegisterGeneral Purpose Input/Output Pin Control Register GPO Cleared by writing a logic 1 into the Iclr control bit Interrupt Status. When this bit is high a Tick TimerInterrupt is being generated at the level programmed Writing a 1 to this bit clears bits 25 through 28 LTO SCC Error Status and Interrupt Control RegistersSCC Error Status Register SCL R IRQ SCC Modem Interrupt Control RegisterAvec SCC Transmit Interrupt Control Register SCC Receive Interrupt Control Register Modem Piack Register Transmit Piack Register Receive Piack Register Writing a 1 to this bit clears bits 25 through 27 LTO Lanc Error Status and Interrupt Control RegistersLanc Error Status Register Sclr This status bit reflects the state of the INT pin from Lanc qualified by the IEN bit. When this bit is high, a82596CA Lanc Interrupt Control Register Interrupt level for the 82596CA LANC. Level 0 does not IL2-IL0 if nonzero Lanc Bus Error Interrupt Control RegisterSC0 pins, when the 82596CA Lanc performs Interrupt level. Level 0 does not generate an interrupt Scsi Error Status Register Programming the Scsi Error Status and Interrupt Registers Interrupt level for the Scsi Processor. Level 0 does not Scsi Interrupt Control Register IL2-IL0 Programming the Printer PortPrinter ACK Interrupt Control Register When this bit is high, a printer Fault interrupt is being Printer Fault Interrupt Control RegisterFAULT. Level 0 does not generate an interrupt SEL. Level 0 does not generate an interrupt When this bit is high, a printer SEL interrupt is beingPrinter SEL Interrupt Control Register PE. Level 0 does not generate an interrupt When this bit is high, a printer PE interrupt is beingPrinter PE Interrupt Control Register BUSY. Level 0 does not generate an interrupt When this bit is high, a printer Busy interrupt is beingPrinter Busy Interrupt Control Register Printer Input Status Register STB Printer Port Control RegisterMAN Chip Speed Register INPDoen Printer Data Register Priority Level Comments Interrupt Priority Level Register MSK2 MSK1 MSK0 Interrupt Mask Level Register PCCchip2 Computer Group Literature Center Web Site Mcecc Functions Mcecc Functions on the Petra Asic FeaturesMcecc functions now implemented on the Petra chip include Performance Memory System Cycle Timing Cache Coherency Cycle Types Error ReportingSingle Bit Error Cycle Type = Burst Read or Non-Burst Read Cycle Type = Burst Write Double Bit Error Cycle Type = Burst Read or Non-Burst ReadSingle Bit Error Cycle Type = Non-Burst Write Double Bit Error Cycle Type = Non-Burst Write Triple or Greater Bit Error Cycle Type = Scrub Triple or Greater Bit Error Cycle Type = Non-Burst WriteSingle Bit Error Cycle Type = Scrub Double Bit Error Cycle Type = Scrub Refresh Error LoggingScrub Arbitration Chip Defaults Programming Model Name D31 D30 D29 D28 D27 D26 D25 D24 Mcecc Sector Internal Register Memory Map RWB7 RWB6 1st $FFF43000/2nd $FFF43100 8-bits Memory Size Memory Configuration RegisterMSIZ2-MSIZ0 Bit assignments for the Dram Control register are Base Address RegisterDram Control Register Bclk Frequency Register Data Control Register Unchanged by software or local reset Mcecc Functions RWB0 RWB0 is a general-purpose read/write bit Scrub Control Register This register contains bits 7-0 of the Scrub Period register Scrub Period Register Bits STOFF2-STOFF0 Chip Prescaler CounterScrub Time On/Time Off Register Scrubber Time On STON2-STON0Scrubber Time Off Scrub Prescaler Counter Bits Scrub Timer Counter Bits Scrub Address Counter Bits 1st $FFF43050/2nd $FFF43150 8-bits Error Logger Register Error Address Bits 1st $FFF43068/2nd $FFF43168 8-bits RSIZ2-RSIZ0 Error Syndrome RegisterDefaults Register Dram Array Size SELI1, SELI0 RESST2-RESST0 SDCFG2-SDCFG0 Sdram Configuration Register Initialization Programming Model Syndrome Bit Encoding Syndrome Decoding Error Identifying Sdram Bank in Error Mcecc Functions Computer Group Literature Center Web Site Function Previous Implementation MVME1x2P2 Implementation Table A-1. List of Changes Summary of Changes Computer Group Literature Center Web Site Name Number Connection Diagrams Figure B-1. MVME1X7P Printer Port with MVME712M Figure B-2. MVME1X7P Serial Port 1 Configured as DCE Figure B-3. MVME1X7P Serial Port 2 Configured as DCE Figure B-4. MVME1X7P Serial Port 3 Configured as DCE Figure B-5. MVME1X7P Serial Port 4 Configured as DCE Figure B-6. MVME1X7P Serial Port 1 Configured as DTE Figure B-7. MVME1X7P Serial Port 2 Configured as DTE Figure B-8. MVME1X7P Serial Port 3 Configured as DTE Figure B-9. MVME1X7P Serial Port 4 Configured as DTE Document Title Motorola Publication Number MCG DocumentsTable C-1. Motorola Computer Group Documents Document Title and Source Publication Number Manufacturers’ DocumentsTable C-2. Manufacturers’ Documents Publication Document Title and Source Number Related SpecificationsTable C-3. Related Specifications IEC 821 BUS Index Bbram 10,2-51 Gcsr IN-5 LAN IN-7 MVME1X7P IN-9 SCC Scsi IN-12 Enabling 2-32,2-35,2-43,2-44,2-50,2-51 Index