Motorola MVME1X7P manual Mcecc Functions

MCECC Functions

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Introduction

The ECC DRAM Controller ASIC (MCECC) is a device used on earlier MVME167/177 models whose functions are now incorporated into the Petra chip on the MVME1x7. The two memory controllers modeled in Petra duplicate the functionality of the “parity memory controller” found in MC ASICs as well as that of the “single-bit error correcting/double-bit error detecting” memory controller found in MCECC ASICs.

For ease of use in conjunction with processes, programming models and documentation developed for earlier boards, the structure of this manual preserves the functional distinctions that formerly characterized the MCECC ASIC. This chapter describes the Petra chip as used in the MVME1x7 MCECC implementation.

The MCECC ASICs, used in a set of two, provided the interface to a 144- bit wide DRAM memory array. The Petra implementation provides an interface to a 40-bit SDRAM memory array. There are 32 bits for data, 7 for check bits, and one bit that is not used. SDRAM configurations that allow array sizes of 16MB to 128MB are supported. For a complete description of the memory configurations that are supported, refer to the definition of the SDCFG2-SDCFG0 bits in the SDRAM Configuration register.

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