Cycle Types, Error Reporting | Motorola MVME1X7P specs

Functional Description

ECC

The Petra MCECC sector pair performs single-bit error correction and double-bit error detection (SECDED). Since the SDRAM device can deliver data from incremental addresses with each clock tick (subject to boundary limitations), the Petra MCECC sector does not implement an interleaved memory architecture. The SDRAM array is 32 data bits plus seven checkbits wide. The depth is dependent on the number and type of SDRAM devices.

Cycle Types

The Petra MCECC sector always initiates burst read/write accesses to the SDRAM device. If the bus access is not a burst, the cycle is terminated early. Single- and double-byte write cycles are read-modify-write accesses, but longword write accesses require no read cycle.

Error Reporting

The Petra MCECC sector generates ECC check bits for write cycles. It also checks read data from the DRAM and corrects the data if it contains a single-bit error. If a non-correctable error occurs within the read data, the Petra MCECC sector so indicates by asserting its non-correctable error (NCE∗) pin.

The following paragraphs describe the actions that the MCECC sector will take in different error situations.

Single Bit Error (Cycle Type = Burst Read or Non-Burst Read)

1.Correct the data that is driven to the local MC680x0 bus.

2.Do not correct the data in DRAM. The DRAM is not corrected until the next scrub of that address, which happens only if scrubbing is enabled.

3.Terminate the cycle normally. (Assert TA∗ to the local bus.)

4.Log the error if not already logged.

5.Notify the local MPU via interrupt, if so enabled.

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Motorola MVME1X7P manual Cycle Types, Error Reporting, Single Bit Error Cycle Type = Burst Read or Non-Burst Read

Contents

MVME1X7P Single-Board Computer Programmer’s Reference GuidePage Safety Summary Flammability CE Notice European Community Limited and Restricted Rights Legend Contents Viii VMEchip2 Page Page PCCchip2 Xiii Chapter Appendix a Summary of Changes Xvi List of Figures Xviii List of Tables Page About This Manual Model Number Characteristics Comments and Suggestions Overview of Contents Conventions Used in This Manual Ctrl CR represents the carriage return or Enter key Xxv Xxvi Petra Asic and Second-Generation MVME1X7 Boards Introduction Programming Issues MVME1X7P Features Summary FeaturesFeature Applicable Industry Standards Block Diagram MVME167P Block Diagram MVME177P Block Diagram Data Bus Structure Programming Interfaces Model Sockets Banks EEPROMs on the MVME1X7P MVME177 Flash Memory on the MVME177 Sram Onboard Sdram VMEbus Interface Battery-Backed-Up RAM and ClockInterfaces Serial Port Interface Parallel Printer Interface Ethernet Interface Local Resources Programmable Tick TimersScsi Interface Local Bus Timeout Watchdog TimerFunctional Description Software-Programmable Hardware Interrupts VMEchip2 General-Purpose I/O VMEbus Interface and VMEchip2Petra/VMEchip2 Redundant Logic VMEchip2 Petra Chip Address Bit # Functions Duplicated in VMEchip2 and Petra ASICs Local Bus Memory Map Memory MapsNormal Address Range Local Bus Memory Map Local I/O Devices Memory Map Address Range Devices Accessed Port Size 3KB Programming Issues Tables 1-5 through 1-14 give the detailed memory maps for Detailed I/O Memory Maps Offset VMEchip2 Memory Map Sheet 1 This sheet begins on facing PRE VMEchip2 Memory Map Sheet 2 Compare Register Counter Overflow Offsets Bit Numbers VMEchip2 Memory Map Sheet 3 Printer Memory Map SCC Transmit Piack PCCchip2 Memory Map Vector Base Register Mcecc Base Address = $FFF43000 1st $FFF43100 2nd Mcecc Internal Register Memory MapRegister Bit Names D31 D30 D29 D28 D27 D26 D25 D24 Register Register Bit Names Option Registers Cirrus Logic CD2401 Serial Port Memory Map Interrupt Registers Channel Command and Status RegistersReceive Interrupt Registers Modem Interrupt Registers Transmit Interrupt RegistersDMA Registers DMA Receive Registers DMA Transmit Registers Timer Registers 10 CA Ethernet LAN Memory Map BBRAM/TOD Clock Memory Map 11 C710 Scsi Memory Map 12. M48T58 BBRAM,TOD Clock Memory Map 13. Bbram Configuration Area Memory MapAddress Range Description Size Bytes Address Data Bits Function 14. TOD Clock Memory Map MVME167P-24SE 01-W3620F35C VMEbus Memory Map VMEbus Accesses to the Local BusInterrupt Acknowledge Map VMEbus Short I/O Memory Map Interrupt Handling Example VMEchip2 Tick Timer 1 Periodic Interrupt To the Tick Timer 1 Compare Register description Cache Coherency MVME167P Cache Coherency MVME177P Using Bus Timers 15. Single-Cycle Instructions Indivisible CyclesInstructions Supervisor Stack Pointer MC68060 Local Bus Timeout Sources of Local Bus ErrorsVMEbus Access Timeout VMEbus Berr Bus Error Processing Error ConditionsVMEchip2 MPU Offboard Error MPU Parity ErrorMPU TEA Cause Unidentified Dmac Parity Error Dmac VMEbus ErrorMPU Local Bus Time-out Dmac LTO Error Dmac Offboard Error Dmac TEA Cause Unidentified SCC Retry Error SCC Offboard Error SCC Parity Error LAN Parity Error SCC LTO ErrorLAN Offboard Error Scsi Parity Error LAN LTO ErrorScsi Offboard Error Scsi LTO Error Programming Issues Computer Group Literature Center Web Site Function Features Features of the VMEchip2 Asic VMEchip2 Introduction Local-Bus-to-VMEbus Interface Functional Blocks VMEchip2 Block Diagram VMEchip2 Local-Bus-to-VMEbus Requester VMEchip2 Functional Blocks VMEbus-to-Local-Bus Interface Local-Bus-to-VMEbus DMA Controller Functional Blocks No-Address-Increment DMA Transfers Dmac VMEbus Requester Prescaler Tick and Watchdog Timers Tick Timers VMEbus Interrupter VMEbus System Controller Bus TimerArbiter Iack Daisy-Chain Driver Local Bus Interrupter and Interrupt Handler Reset DriverDmac done VMEbus Sysfail interrupter Functional Blocks Global Control and Status Registers Lcsr Programming Model 2shows a summary of the LCSRs State of the bit following a reset, defined as follows VMEchip2 Memory Map-LCSR Summary Sheet 1 IO2 IO1 VMEchip2 Memory Map-LCSR Summary Sheet 2 IRQ7 IRQ6 IRQ5 Programming the VMEbus Slave Map Decoders Lcsr Programming Model VMEbus Slave Starting Address Register VMEbus Slave Ending Address Register VMEbus Slave Address Translation Address Offset Register Local-bus map decoder Segment Address Translation Size Select Value VMEbus Slave Address Translation Select Register $FFF4000C 16 bits WP2 VMEbus Slave Write Post and Snoop Control RegisterSNP2 DAT VMEbus Slave Address Modifier Select RegisterPGM BLK SUP USR SNP1 WP1 Block access cycles When this bit is high, the first map decoder responds toA24 access cycles Cycles VMEbus supervisory access cycles. When this bit is low A32 access cyclesProgramming the Local-Bus-to-VMEbus Map Decoders Bit is low, the first map decoder does not respond to VMEchip2 Local Bus Slave VMEbus Master Ending Address Register Local Bus Slave VMEbus Master Starting Address Register $FFF4001C 16 bits $FFF40024 16 bits Local Bus Slave VMEbus Master Attribute Register Decoder 3. Because the local-bus-to-VMEbus interface Segment defined by map decoder 3. When this bit is Decoder 2. Since the local-bus-to-VMEbus interface does Segment defined by map decoder 2. When this bit isNot support block transfers, the block transfer address Decoder 1. Because the local-bus-to-VMEbus interface Segment defined by map decoder 1. When this bit is VMEbus Slave Gcsr Group Address Register VMEbus Slave Gcsr Board Address Register EN1 Local-Bus-to-VMEbus Enable Control RegisterEN2 EN3 Local-Bus-to-VMEbus I/O Control Register I2WP Programming the VMEchip2 DMA ControllerI2EN ROM Control Register VMEchip2 Dmac Registers Dmac Command Packet FormatEprom Decoder, Sram and DMA Control Register Entry Function ROM0 Tblsc Lvfair LvrwdDWB DHB Dfair DrelmDtbl DEN Tvme Dmac Control Register 2 bitsLinc Vinc Modified when the Dmac loads the control register from This bit is used only in command chaining mode. It is onlyControl word in the command packet. When this bit SNP Dmac Local Bus Address Counter Dmac Byte Counter Dmac VMEbus Address CounterTable Address Counter Dmac VMEbus Address Counter Irql VMEbus Interrupter Control RegisterIrqs Irqc MPU Status and DMA Interrupt Count Register VMEbus Interrupter Vector Register Dmac Status Register VMEbus Arbiter Time-Out Control Register Programming the Tick and Watchdog Timers Time on Vgto Vato Lbto Prescaler register = 256- Bclock MHz Prescaler Control Register Tick Timer 1 Counter Tick Timer 1 Compare Register Tick Timer 2 Counter Tick Timer 2 Compare RegisterTick timer 2 Counter Board Control Register Wden Watchdog Timer Control RegisterWDS/L Tick Timer 2 Control Register Prescaler Counter Tick Timer 1 Control Register Programming the Local Bus Interrupter Interrupt Vector Priority for Simultaneous Interrupts Local Bus Interrupter Summary Dmac Local Bus Interrupter Status Register bits LM1 LM0SIG0 SIG1 SW1 SW0SW2 SW3 VME2 VME1VME3 VME4 Local Bus Interrupter Enable Register bits ELM1 ELM0ESIG0 ESIG1 ESW1 ESW0ESW2 ESW3 EIRQ2 EIRQ1EIRQ3 EIRQ4 Software Interrupt Set Register bits Interrupt Clear Register bits Interrupt Level Register 1 bits IRQ1E Level These bits define the level of the tick timer 2 interrupt These bits define the level of the tick timer 1 interruptInterrupt Level Register 2 bits SIG3 Level SIG2 Level Interrupt Level Register 3 bits SW5 Level SW4 Level VIRQ7 Level Interrupt Level Register 4 bitsThese bits define the level of the VMEbus IRQ7 interrupt Spare Level VIRQ3 Level Interrupts may be mapped to any local bus interrupt levelThese bits define the level of the VMEbus IRQ3 interrupt VIRQ4 Level VIRQ2 Level VIRQ1 LevelVBR Control Register Connects to pin 17 of the Remote Status and Control Connects to pin 16 of the Remote Status and ControlConnects to pin 18 of the Remote Status and Control Not used Enint Miscellaneous Control Register Lcsr Programming Model Gcsr Programming Model 101 Programming the Gcsr VMEchip2 Memory Map Gcsr Summary 5shows a summary of the GcsrVMEchip2 Revision Register Offsets Bit Numbers Loca VMEchip2 LM/SIG Register VMEchip2 ID Register LM3 LM2 ISF VMEchip2 Board Status/Control RegisterRST General Purpose Register Local Bus $FFF40114/VMEbus $XXYA 16 bits PCCchip2 Summary of Major Features General Description PCCchip2 Block Diagram 82596CA LAN Controller Interface Bbram InterfaceMPU Port and MPU Channel Attention MC68040-Bus Master Support for 82596CA Lanc Bus Error Lanc Interrupt Parallel Port Interface 53C710 Scsi Controller Interface CD2401 SCC Interface General Purpose I/O Pin PCCchip2 Tick Timer PCCchip2 Devices Memory Map Overall Memory MapAddress Range Selected Device Comments Summary of the PCCchip2 CSR is shown in Table Programming Model PCCchip2 Memory Map Control and Status Registers Fast Chip Revision Register Chip ID Register Fast General Control Register DR0 Vector Base Register Gpio IRQ Interrupt Source IV3-IV0 Priority Programming the Tick Timers Tick Timer 2 Compare Register Prescaler Count Register Prescaler Clock Adjust Register Prescaler clock adjust register = 256 Bclk MHz When this bit is low, the counter is not reset Clear On Compare. When this bit is high, the counter isCEN $FFF42017 8 bits Iclr General Purpose Input Interrupt Control RegisterIEN INT General Purpose Input/Output Pin Control Register Tick Timer 2 Interrupt Control RegisterGPO Gpoe Interrupt is being generated at the level programmed Interrupt Status. When this bit is high a Tick TimerCleared by writing a logic 1 into the Iclr control bit SCC Error Status Register SCC Error Status and Interrupt Control RegistersSCL R Writing a 1 to this bit clears bits 25 through 28 LTO Avec SCC Modem Interrupt Control RegisterIRQ SCC Transmit Interrupt Control Register SCC Receive Interrupt Control Register Modem Piack Register Transmit Piack Register Receive Piack Register Lanc Error Status Register Lanc Error Status and Interrupt Control RegistersSclr Writing a 1 to this bit clears bits 25 through 27 LTO 82596CA Lanc Interrupt Control Register Lanc qualified by the IEN bit. When this bit is high, aInterrupt level for the 82596CA LANC. Level 0 does not This status bit reflects the state of the INT pin from SC0 pins, when the 82596CA Lanc performs Lanc Bus Error Interrupt Control RegisterInterrupt level. Level 0 does not generate an interrupt IL2-IL0 if nonzero Scsi Error Status Register Programming the Scsi Error Status and Interrupt Registers Interrupt level for the Scsi Processor. Level 0 does not Scsi Interrupt Control Register Printer ACK Interrupt Control Register Programming the Printer PortIL2-IL0 FAULT. Level 0 does not generate an interrupt Printer Fault Interrupt Control RegisterWhen this bit is high, a printer Fault interrupt is being Printer SEL Interrupt Control Register When this bit is high, a printer SEL interrupt is beingSEL. Level 0 does not generate an interrupt Printer PE Interrupt Control Register When this bit is high, a printer PE interrupt is beingPE. Level 0 does not generate an interrupt Printer Busy Interrupt Control Register When this bit is high, a printer Busy interrupt is beingBUSY. Level 0 does not generate an interrupt Printer Input Status Register MAN Printer Port Control RegisterSTB Doen INPChip Speed Register Printer Data Register Priority Level Comments Interrupt Priority Level Register MSK2 MSK1 MSK0 Interrupt Mask Level Register PCCchip2 Computer Group Literature Center Web Site Mcecc Functions Mcecc functions now implemented on the Petra chip include FeaturesMcecc Functions on the Petra Asic Performance Memory System Cycle Timing Cache Coherency Single Bit Error Cycle Type = Burst Read or Non-Burst Read Error ReportingCycle Types Single Bit Error Cycle Type = Non-Burst Write Double Bit Error Cycle Type = Burst Read or Non-Burst ReadDouble Bit Error Cycle Type = Non-Burst Write Cycle Type = Burst Write Single Bit Error Cycle Type = Scrub Triple or Greater Bit Error Cycle Type = Non-Burst WriteDouble Bit Error Cycle Type = Scrub Triple or Greater Bit Error Cycle Type = Scrub Scrub Error LoggingRefresh Arbitration Chip Defaults Programming Model Name D31 D30 D29 D28 D27 D26 D25 D24 Mcecc Sector Internal Register Memory Map RWB7 RWB6 1st $FFF43000/2nd $FFF43100 8-bits MSIZ2-MSIZ0 Memory Configuration RegisterMemory Size Dram Control Register Base Address RegisterBit assignments for the Dram Control register are Bclk Frequency Register Data Control Register Unchanged by software or local reset Mcecc Functions RWB0 RWB0 is a general-purpose read/write bit Scrub Control Register This register contains bits 7-0 of the Scrub Period register Scrub Period Register Bits Scrub Time On/Time Off Register Chip Prescaler CounterSTOFF2-STOFF0 Scrubber Time Off STON2-STON0Scrubber Time On Scrub Prescaler Counter Bits Scrub Timer Counter Bits Scrub Address Counter Bits 1st $FFF43050/2nd $FFF43150 8-bits Error Logger Register Error Address Bits 1st $FFF43068/2nd $FFF43168 8-bits Defaults Register Error Syndrome RegisterRSIZ2-RSIZ0 Dram Array Size SELI1, SELI0 RESST2-RESST0 SDCFG2-SDCFG0 Sdram Configuration Register Initialization Programming Model Syndrome Bit Encoding Syndrome Decoding Error Identifying Sdram Bank in Error Mcecc Functions Computer Group Literature Center Web Site Function Previous Implementation MVME1x2P2 Implementation Table A-1. List of Changes Summary of Changes Computer Group Literature Center Web Site Name Number Connection Diagrams Figure B-1. MVME1X7P Printer Port with MVME712M Figure B-2. MVME1X7P Serial Port 1 Configured as DCE Figure B-3. MVME1X7P Serial Port 2 Configured as DCE Figure B-4. MVME1X7P Serial Port 3 Configured as DCE Figure B-5. MVME1X7P Serial Port 4 Configured as DCE Figure B-6. MVME1X7P Serial Port 1 Configured as DTE Figure B-7. MVME1X7P Serial Port 2 Configured as DTE Figure B-8. MVME1X7P Serial Port 3 Configured as DTE Figure B-9. MVME1X7P Serial Port 4 Configured as DTE Table C-1. Motorola Computer Group Documents MCG DocumentsDocument Title Motorola Publication Number Table C-2. Manufacturers’ Documents Manufacturers’ DocumentsDocument Title and Source Publication Number Table C-3. Related Specifications Related SpecificationsPublication Document Title and Source Number IEC 821 BUS Index Bbram 10,2-51 Gcsr IN-5 LAN IN-7 MVME1X7P IN-9 SCC Scsi IN-12 Enabling 2-32,2-35,2-43,2-44,2-50,2-51 Index