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Motorola MVME1X7P manual SCC Transmit Interrupt Control Register

Models: MVME1X7P

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Programming Model

SCC Transmit Interrupt Control Register

ADR/SIZ

$FFF4201E (8 bits)

BIT

15

14

13

12

11

10

9

8

NAME

IRQ

IEN

AVEC

IL2

IL1

IL0

OPER

R

R

R

R/W

R/W

R/W

R/W

R/W

RESET

0

0

X

0 PL

0 PL

0 PL

0 PL

0 PL

IL2-IL0

Interrupt Request Level. These three bits select the

interrupt level for SCC Transmit Interrupt. Level 0 does

not generate an interrupt.

AVEC

When this bit is high, the PCCchip2 supplies the interrupt

vector to the MPU during an IACK for SCC transmit

interrupt. When this bit is low, the PCCchip2 obtains the

vector from the SCC and passes it to the MPU. The use of

the AVEC mode is not recommended.

IEN

Interrupt Enable. When this bit is high, the interrupt is

enabled. The interrupt is disabled when this bit is low.

IRQ

Interrupt Status. This status bit reflects the state of the

SCC-IRQ2 pin of the CD2401 (qualified by the IEN bit).

When this bit is high, an SCC Transmit interrupt is being

generated at the level programmed in IL2-IL0 (if

nonzero). This status bit does not need to be cleared,

because it is not edge-sensitive.

3

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Motorola MVME1X7P manual SCC Transmit Interrupt Control Register

Contents

MVME1X7P Single-Board Computer Programmer’s Reference GuidePage Safety Summary Flammability CE Notice European Community Limited and Restricted Rights Legend Contents Viii VMEchip2 Page Page PCCchip2 Xiii Chapter Appendix a Summary of Changes Xvi List of Figures Xviii List of Tables Page About This Manual Model Number CharacteristicsComments and Suggestions Overview of ContentsConventions Used in This Manual Ctrl CR represents the carriage return or Enter keyXxv Xxvi Petra Asic and Second-Generation MVME1X7 Boards IntroductionProgramming Issues Feature FeaturesMVME1X7P Features Summary Applicable Industry Standards Block DiagramMVME167P Block Diagram MVME177P Block Diagram Data Bus Structure Programming InterfacesModel Sockets Banks EEPROMs on the MVME1X7PMVME177 Flash Memory on the MVME177Sram Onboard Sdram Interfaces Battery-Backed-Up RAM and ClockVMEbus Interface Serial Port Interface Parallel Printer Interface Ethernet Interface Scsi Interface Programmable Tick TimersLocal Resources Software-Programmable Hardware Interrupts Watchdog TimerLocal Bus Timeout Functional DescriptionPetra/VMEchip2 Redundant Logic VMEbus Interface and VMEchip2VMEchip2 General-Purpose I/O VMEchip2 Petra Chip Address Bit # Functions Duplicated in VMEchip2 and Petra ASICsNormal Address Range Memory MapsLocal Bus Memory Map Local Bus Memory Map Local I/O Devices Memory Map Address Range Devices Accessed Port Size3KB Programming Issues Tables 1-5 through 1-14 give the detailed memory maps for Detailed I/O Memory MapsOffset VMEchip2 Memory Map Sheet 1This sheet begins on facing PRE VMEchip2 Memory Map Sheet 2Compare Register Counter Overflow Offsets Bit Numbers VMEchip2 Memory Map Sheet 3Printer Memory Map SCC Transmit Piack PCCchip2 Memory MapVector Base Register D31 D30 D29 D28 D27 D26 D25 D24 Mcecc Internal Register Memory MapMcecc Base Address = $FFF43000 1st $FFF43100 2nd Register Bit NamesRegister Register Bit Names Option Registers Cirrus Logic CD2401 Serial Port Memory MapReceive Interrupt Registers Channel Command and Status RegistersInterrupt Registers DMA Receive Registers Transmit Interrupt RegistersModem Interrupt Registers DMA RegistersDMA Transmit Registers Timer Registers10 CA Ethernet LAN Memory Map BBRAM/TOD Clock Memory Map 11 C710 Scsi Memory MapAddress Range Description Size Bytes 13. Bbram Configuration Area Memory Map12. M48T58 BBRAM,TOD Clock Memory Map Address Data Bits Function 14. TOD Clock Memory MapMVME167P-24SE 01-W3620F35C VMEbus Short I/O Memory Map VMEbus Accesses to the Local BusVMEbus Memory Map Interrupt Acknowledge MapInterrupt Handling Example VMEchip2 Tick Timer 1 Periodic InterruptTo the Tick Timer 1 Compare Register description Cache Coherency MVME167P Cache Coherency MVME177P Using Bus Timers Instructions Indivisible Cycles15. Single-Cycle Instructions Supervisor Stack Pointer MC68060 VMEbus Berr Sources of Local Bus ErrorsLocal Bus Timeout VMEbus Access TimeoutVMEchip2 Error ConditionsBus Error Processing MPU TEA Cause Unidentified MPU Parity ErrorMPU Offboard Error MPU Local Bus Time-out Dmac VMEbus ErrorDmac Parity Error Dmac LTO Error Dmac Offboard ErrorDmac TEA Cause Unidentified SCC Retry ErrorSCC Offboard Error SCC Parity ErrorLAN Offboard Error SCC LTO ErrorLAN Parity Error Scsi Offboard Error LAN LTO ErrorScsi Parity Error Scsi LTO Error Programming Issues Computer Group Literature Center Web Site Function Features Features of the VMEchip2 AsicVMEchip2 Introduction Local-Bus-to-VMEbus Interface Functional BlocksVMEchip2 Block Diagram VMEchip2 Local-Bus-to-VMEbus Requester VMEchip2 Functional Blocks VMEbus-to-Local-Bus InterfaceLocal-Bus-to-VMEbus DMA Controller Functional Blocks No-Address-Increment DMA Transfers Dmac VMEbus Requester Prescaler Tick and Watchdog TimersTick Timers VMEbus Interrupter Iack Daisy-Chain Driver Bus TimerVMEbus System Controller ArbiterVMEbus Sysfail interrupter Reset DriverLocal Bus Interrupter and Interrupt Handler Dmac doneFunctional Blocks Global Control and Status Registers Lcsr Programming Model2shows a summary of the LCSRs State of the bit following a reset, defined as followsVMEchip2 Memory Map-LCSR Summary Sheet 1 IO2 IO1 VMEchip2 Memory Map-LCSR Summary Sheet 2 IRQ7 IRQ6 IRQ5 Programming the VMEbus Slave Map Decoders Lcsr Programming Model VMEbus Slave Starting Address Register VMEbus Slave Ending Address RegisterVMEbus Slave Address Translation Address Offset Register Local-bus map decoderSegment Address Translation Size Select Value VMEbus Slave Address Translation Select Register$FFF4000C 16 bits SNP2 VMEbus Slave Write Post and Snoop Control RegisterWP2 BLK VMEbus Slave Address Modifier Select RegisterDAT PGMSUP USRSNP1 WP1Cycles When this bit is high, the first map decoder responds toBlock access cycles A24 access cyclesBit is low, the first map decoder does not respond to A32 access cyclesVMEbus supervisory access cycles. When this bit is low Programming the Local-Bus-to-VMEbus Map DecodersVMEchip2 Local Bus Slave VMEbus Master Ending Address Register Local Bus Slave VMEbus Master Starting Address Register $FFF4001C 16 bits $FFF40024 16 bits Local Bus Slave VMEbus Master Attribute Register Decoder 3. Because the local-bus-to-VMEbus interface Segment defined by map decoder 3. When this bit isNot support block transfers, the block transfer address Segment defined by map decoder 2. When this bit isDecoder 2. Since the local-bus-to-VMEbus interface does Decoder 1. Because the local-bus-to-VMEbus interface Segment defined by map decoder 1. When this bit isVMEbus Slave Gcsr Group Address Register VMEbus Slave Gcsr Board Address Register EN3 Local-Bus-to-VMEbus Enable Control RegisterEN1 EN2Local-Bus-to-VMEbus I/O Control Register ROM Control Register Programming the VMEchip2 DMA ControllerI2WP I2ENVMEchip2 Entry Function Dmac Command Packet FormatDmac Registers Eprom Decoder, Sram and DMA Control RegisterROM0 TblscDHB LvrwdLvfair DWBDEN DrelmDfair DtblVinc Dmac Control Register 2 bitsTvme LincSNP This bit is used only in command chaining mode. It is onlyModified when the Dmac loads the control register from Control word in the command packet. When this bitDmac Local Bus Address Counter Dmac VMEbus Address Counter Dmac VMEbus Address CounterDmac Byte Counter Table Address CounterIrqc VMEbus Interrupter Control RegisterIrql IrqsMPU Status and DMA Interrupt Count Register VMEbus Interrupter Vector RegisterDmac Status Register VMEbus Arbiter Time-Out Control Register Programming the Tick and Watchdog TimersTime on VgtoVato LbtoPrescaler register = 256- Bclock MHz Prescaler Control RegisterTick Timer 1 Counter Tick Timer 1 Compare RegisterTick timer 2 Counter Tick Timer 2 Compare RegisterTick Timer 2 Counter Board Control Register WDS/L Watchdog Timer Control RegisterWden Tick Timer 2 Control Register Prescaler Counter Tick Timer 1 Control RegisterProgramming the Local Bus Interrupter Interrupt Vector Priority for Simultaneous Interrupts Local Bus Interrupter SummaryDmac Local Bus Interrupter Status Register bits SIG1 LM0LM1 SIG0SW3 SW0SW1 SW2VME4 VME1VME2 VME3Local Bus Interrupter Enable Register bits ESIG1 ELM0ELM1 ESIG0ESW3 ESW0ESW1 ESW2EIRQ4 EIRQ1EIRQ2 EIRQ3Software Interrupt Set Register bits Interrupt Clear Register bits Interrupt Level Register 1 bits IRQ1E Level Interrupt Level Register 2 bits These bits define the level of the tick timer 1 interruptThese bits define the level of the tick timer 2 interrupt SIG3 Level SIG2 Level Interrupt Level Register 3 bits SW5 Level SW4 Level Spare Level Interrupt Level Register 4 bitsVIRQ7 Level These bits define the level of the VMEbus IRQ7 interruptVIRQ4 Level Interrupts may be mapped to any local bus interrupt levelVIRQ3 Level These bits define the level of the VMEbus IRQ3 interruptVBR VIRQ1 LevelVIRQ2 Level Control Register Not used Connects to pin 16 of the Remote Status and ControlConnects to pin 17 of the Remote Status and Control Connects to pin 18 of the Remote Status and ControlEnint Miscellaneous Control RegisterLcsr Programming Model Gcsr Programming Model 101 Programming the Gcsr Offsets Bit Numbers Loca 5shows a summary of the GcsrVMEchip2 Memory Map Gcsr Summary VMEchip2 Revision RegisterVMEchip2 LM/SIG Register VMEchip2 ID RegisterLM3 LM2RST VMEchip2 Board Status/Control RegisterISF General Purpose Register Local Bus $FFF40114/VMEbus $XXYA 16 bits PCCchip2 Summary of Major FeaturesGeneral Description PCCchip2 Block DiagramMPU Port and MPU Channel Attention Bbram Interface82596CA LAN Controller Interface MC68040-Bus Master Support for 82596CA Lanc Bus ErrorLanc Interrupt Parallel Port Interface 53C710 Scsi Controller InterfaceCD2401 SCC Interface General Purpose I/O PinPCCchip2 Tick Timer Address Range Selected Device Comments Overall Memory MapPCCchip2 Devices Memory Map Summary of the PCCchip2 CSR is shown in Table Programming ModelPCCchip2 Memory Map Control and Status Registers Fast Chip Revision Register Chip ID RegisterFast General Control RegisterDR0 Vector Base RegisterGpio IRQ Interrupt Source IV3-IV0 PriorityProgramming the Tick Timers Tick Timer 2 Compare Register Prescaler Count Register Prescaler Clock Adjust RegisterPrescaler clock adjust register = 256 Bclk MHz CEN Clear On Compare. When this bit is high, the counter isWhen this bit is low, the counter is not reset $FFF42017 8 bits INT General Purpose Input Interrupt Control RegisterIclr IENGpoe Tick Timer 2 Interrupt Control RegisterGeneral Purpose Input/Output Pin Control Register GPOCleared by writing a logic 1 into the Iclr control bit Interrupt Status. When this bit is high a Tick TimerInterrupt is being generated at the level programmed Writing a 1 to this bit clears bits 25 through 28 LTO SCC Error Status and Interrupt Control RegistersSCC Error Status Register SCL RIRQ SCC Modem Interrupt Control RegisterAvec SCC Transmit Interrupt Control Register SCC Receive Interrupt Control Register Modem Piack Register Transmit Piack Register Receive Piack Register Writing a 1 to this bit clears bits 25 through 27 LTO Lanc Error Status and Interrupt Control RegistersLanc Error Status Register SclrThis status bit reflects the state of the INT pin from Lanc qualified by the IEN bit. When this bit is high, a82596CA Lanc Interrupt Control Register Interrupt level for the 82596CA LANC. Level 0 does notIL2-IL0 if nonzero Lanc Bus Error Interrupt Control RegisterSC0 pins, when the 82596CA Lanc performs Interrupt level. Level 0 does not generate an interruptScsi Error Status Register Programming the Scsi Error Status and Interrupt RegistersInterrupt level for the Scsi Processor. Level 0 does not Scsi Interrupt Control RegisterIL2-IL0 Programming the Printer PortPrinter ACK Interrupt Control Register When this bit is high, a printer Fault interrupt is being Printer Fault Interrupt Control RegisterFAULT. Level 0 does not generate an interrupt SEL. Level 0 does not generate an interrupt When this bit is high, a printer SEL interrupt is beingPrinter SEL Interrupt Control Register PE. Level 0 does not generate an interrupt When this bit is high, a printer PE interrupt is beingPrinter PE Interrupt Control Register BUSY. Level 0 does not generate an interrupt When this bit is high, a printer Busy interrupt is beingPrinter Busy Interrupt Control Register Printer Input Status Register STB Printer Port Control RegisterMAN Chip Speed Register INPDoen Printer Data Register Priority Level Comments Interrupt Priority Level RegisterMSK2 MSK1 MSK0 Interrupt Mask Level RegisterPCCchip2 Computer Group Literature Center Web Site Mcecc Functions Mcecc Functions on the Petra Asic FeaturesMcecc functions now implemented on the Petra chip include Performance Memory System Cycle Timing Cache CoherencyCycle Types Error ReportingSingle Bit Error Cycle Type = Burst Read or Non-Burst Read Cycle Type = Burst Write Double Bit Error Cycle Type = Burst Read or Non-Burst ReadSingle Bit Error Cycle Type = Non-Burst Write Double Bit Error Cycle Type = Non-Burst WriteTriple or Greater Bit Error Cycle Type = Scrub Triple or Greater Bit Error Cycle Type = Non-Burst WriteSingle Bit Error Cycle Type = Scrub Double Bit Error Cycle Type = ScrubRefresh Error LoggingScrub Arbitration Chip DefaultsProgramming Model Name D31 D30 D29 D28 D27 D26 D25 D24 Mcecc Sector Internal Register Memory MapRWB7 RWB6 1st $FFF43000/2nd $FFF43100 8-bits Memory Size Memory Configuration RegisterMSIZ2-MSIZ0 Bit assignments for the Dram Control register are Base Address RegisterDram Control Register Bclk Frequency Register Data Control Register Unchanged by software or local resetMcecc Functions RWB0 RWB0 is a general-purpose read/write bit Scrub Control RegisterThis register contains bits 7-0 of the Scrub Period register Scrub Period Register BitsSTOFF2-STOFF0 Chip Prescaler CounterScrub Time On/Time Off Register Scrubber Time On STON2-STON0Scrubber Time Off Scrub Prescaler Counter Bits Scrub Timer Counter Bits Scrub Address Counter Bits 1st $FFF43050/2nd $FFF43150 8-bits Error Logger Register Error Address Bits 1st $FFF43068/2nd $FFF43168 8-bits RSIZ2-RSIZ0 Error Syndrome RegisterDefaults Register Dram Array Size SELI1, SELI0RESST2-RESST0 SDCFG2-SDCFG0 Sdram Configuration RegisterInitialization Programming Model Syndrome Bit Encoding Syndrome DecodingError Identifying Sdram Bank in ErrorMcecc Functions Computer Group Literature Center Web Site Function Previous Implementation MVME1x2P2 Implementation Table A-1. List of ChangesSummary of Changes Computer Group Literature Center Web Site Name Number Connection DiagramsFigure B-1. MVME1X7P Printer Port with MVME712M Figure B-2. MVME1X7P Serial Port 1 Configured as DCE Figure B-3. MVME1X7P Serial Port 2 Configured as DCE Figure B-4. MVME1X7P Serial Port 3 Configured as DCE Figure B-5. MVME1X7P Serial Port 4 Configured as DCE Figure B-6. MVME1X7P Serial Port 1 Configured as DTE Figure B-7. MVME1X7P Serial Port 2 Configured as DTE Figure B-8. MVME1X7P Serial Port 3 Configured as DTE Figure B-9. MVME1X7P Serial Port 4 Configured as DTE Document Title Motorola Publication Number MCG DocumentsTable C-1. Motorola Computer Group Documents Document Title and Source Publication Number Manufacturers’ DocumentsTable C-2. Manufacturers’ Documents Publication Document Title and Source Number Related SpecificationsTable C-3. Related Specifications IEC 821 BUS Index Bbram 10,2-51 Gcsr IN-5 LAN IN-7 MVME1X7P IN-9 SCC Scsi IN-12 Enabling 2-32,2-35,2-43,2-44,2-50,2-51 Index