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Motorola MVME1X7P manual VMEchip2

Models: MVME1X7P

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VMEchip2

The requester requests the bus if any of the following conditions occur:

1.The local bus master initiates either a data transfer cycle or an interrupt acknowledge cycle to the VMEbus.

2.The chip is requested to acquire control of the VMEbus as signaled by the DWB input signal pin.

3.The chip is requested to acquire control of the VMEbus as signaled by the DWB control bit in the LCSR.

The local-bus-to-VMEbus requester in the VMEchip2 implements a fair mode. By setting the LVFAIR bit, the requester refrains from requesting the VMEbus until it detects its assigned request line in its negated state.

The local-bus-to-VMEbus requester attempts to release the VMEbus when the requested data transfer operation is complete, the DWB pin is negated, the DWB bit in the LCSR is negated and the bus is not being held by a lock cycle. The requester releases the bus as follows:

1.When the chip is configured in release-when-done (RWD) mode, the requester releases the bus when the above conditions are satisfied.

2.When the chip is configured in release-on-request (ROR) mode, the requester releases the bus when the above conditions are satisfied and there is a bus request pending on one of the VMEbus request lines.

To minimize the timing overhead of the arbitration process, the local-bus- to-VMEbus requester in the VMEchip2 executes an early release of the VMEbus. If it is about to release the bus and it is executing a VMEbus cycle, the requester releases BBSY before its associated master completes the cycle. This allows the arbiter to arbitrate any pending requests, and grant the bus to the next requester, at the same time that the active master completes its cycle.

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Motorola MVME1X7P manual VMEchip2

Contents

Programmer’s Reference Guide MVME1X7P Single-Board ComputerPage Safety Summary Flammability CE Notice European Community Limited and Restricted Rights Legend Contents Viii VMEchip2 Page Page PCCchip2 Xiii Chapter Appendix a Summary of Changes Xvi List of Figures Xviii List of Tables Page Model Number Characteristics About This ManualOverview of Contents Comments and SuggestionsConventions Used in This Manual CR represents the carriage return or Enter key CtrlXxv Xxvi Introduction Petra Asic and Second-Generation MVME1X7 BoardsProgramming Issues Feature FeaturesMVME1X7P Features Summary Block Diagram Applicable Industry StandardsMVME167P Block Diagram MVME177P Block Diagram Programming Interfaces Data Bus StructureEEPROMs on the MVME1X7P Model Sockets BanksFlash Memory on the MVME177 MVME177Sram Onboard Sdram Interfaces Battery-Backed-Up RAM and ClockVMEbus Interface Serial Port Interface Parallel Printer Interface Ethernet Interface Scsi Interface Programmable Tick TimersLocal Resources Functional Description Watchdog TimerLocal Bus Timeout Software-Programmable Hardware InterruptsPetra/VMEchip2 Redundant Logic VMEbus Interface and VMEchip2VMEchip2 General-Purpose I/O Functions Duplicated in VMEchip2 and Petra ASICs VMEchip2 Petra Chip Address Bit #Normal Address Range Memory MapsLocal Bus Memory Map Local Bus Memory Map Address Range Devices Accessed Port Size Local I/O Devices Memory Map3KB Programming Issues Detailed I/O Memory Maps Tables 1-5 through 1-14 give the detailed memory maps forVMEchip2 Memory Map Sheet 1 OffsetThis sheet begins on facing VMEchip2 Memory Map Sheet 2 PRECompare Register Counter Overflow VMEchip2 Memory Map Sheet 3 Offsets Bit NumbersPrinter Memory Map PCCchip2 Memory Map SCC Transmit PiackVector Base Register Register Bit Names Mcecc Internal Register Memory MapMcecc Base Address = $FFF43000 1st $FFF43100 2nd D31 D30 D29 D28 D27 D26 D25 D24Register Register Bit Names Cirrus Logic CD2401 Serial Port Memory Map Option RegistersReceive Interrupt Registers Channel Command and Status RegistersInterrupt Registers DMA Registers Transmit Interrupt RegistersModem Interrupt Registers DMA Receive RegistersTimer Registers DMA Transmit Registers10 CA Ethernet LAN Memory Map 11 C710 Scsi Memory Map BBRAM/TOD Clock Memory MapAddress Range Description Size Bytes 13. Bbram Configuration Area Memory Map12. M48T58 BBRAM,TOD Clock Memory Map 14. TOD Clock Memory Map Address Data Bits FunctionMVME167P-24SE 01-W3620F35C Interrupt Acknowledge Map VMEbus Accesses to the Local BusVMEbus Memory Map VMEbus Short I/O Memory MapExample VMEchip2 Tick Timer 1 Periodic Interrupt Interrupt HandlingTo the Tick Timer 1 Compare Register description Cache Coherency MVME167P Cache Coherency MVME177P Using Bus Timers Instructions Indivisible Cycles15. Single-Cycle Instructions Supervisor Stack Pointer MC68060 VMEbus Access Timeout Sources of Local Bus ErrorsLocal Bus Timeout VMEbus BerrVMEchip2 Error ConditionsBus Error Processing MPU TEA Cause Unidentified MPU Parity ErrorMPU Offboard Error MPU Local Bus Time-out Dmac VMEbus ErrorDmac Parity Error Dmac Offboard Error Dmac LTO ErrorSCC Retry Error Dmac TEA Cause UnidentifiedSCC Parity Error SCC Offboard ErrorLAN Offboard Error SCC LTO ErrorLAN Parity Error Scsi Offboard Error LAN LTO ErrorScsi Parity Error Scsi LTO Error Programming Issues Computer Group Literature Center Web Site Features of the VMEchip2 Asic Function FeaturesVMEchip2 Introduction Functional Blocks Local-Bus-to-VMEbus InterfaceVMEchip2 Block Diagram VMEchip2 Local-Bus-to-VMEbus Requester VMEchip2 VMEbus-to-Local-Bus Interface Functional BlocksLocal-Bus-to-VMEbus DMA Controller Functional Blocks No-Address-Increment DMA Transfers Dmac VMEbus Requester Tick and Watchdog Timers PrescalerTick Timers VMEbus Interrupter Arbiter Bus TimerVMEbus System Controller Iack Daisy-Chain DriverDmac done Reset DriverLocal Bus Interrupter and Interrupt Handler VMEbus Sysfail interrupterFunctional Blocks Lcsr Programming Model Global Control and Status RegistersState of the bit following a reset, defined as follows 2shows a summary of the LCSRsVMEchip2 Memory Map-LCSR Summary Sheet 1 IO2 IO1 VMEchip2 Memory Map-LCSR Summary Sheet 2 IRQ7 IRQ6 IRQ5 Programming the VMEbus Slave Map Decoders Lcsr Programming Model VMEbus Slave Ending Address Register VMEbus Slave Starting Address RegisterLocal-bus map decoder VMEbus Slave Address Translation Address Offset RegisterVMEbus Slave Address Translation Select Register Segment Address Translation Size Select Value$FFF4000C 16 bits SNP2 VMEbus Slave Write Post and Snoop Control RegisterWP2 PGM VMEbus Slave Address Modifier Select RegisterDAT BLKUSR SUPWP1 SNP1A24 access cycles When this bit is high, the first map decoder responds toBlock access cycles CyclesProgramming the Local-Bus-to-VMEbus Map Decoders A32 access cyclesVMEbus supervisory access cycles. When this bit is low Bit is low, the first map decoder does not respond toVMEchip2 Local Bus Slave VMEbus Master Ending Address Register Local Bus Slave VMEbus Master Starting Address Register $FFF4001C 16 bits $FFF40024 16 bits Local Bus Slave VMEbus Master Attribute Register Segment defined by map decoder 3. When this bit is Decoder 3. Because the local-bus-to-VMEbus interfaceNot support block transfers, the block transfer address Segment defined by map decoder 2. When this bit isDecoder 2. Since the local-bus-to-VMEbus interface does Segment defined by map decoder 1. When this bit is Decoder 1. Because the local-bus-to-VMEbus interfaceVMEbus Slave Gcsr Group Address Register VMEbus Slave Gcsr Board Address Register EN2 Local-Bus-to-VMEbus Enable Control RegisterEN1 EN3Local-Bus-to-VMEbus I/O Control Register I2EN Programming the VMEchip2 DMA ControllerI2WP ROM Control RegisterVMEchip2 Eprom Decoder, Sram and DMA Control Register Dmac Command Packet FormatDmac Registers Entry FunctionTblsc ROM0DWB LvrwdLvfair DHBDtbl DrelmDfair DENLinc Dmac Control Register 2 bitsTvme VincControl word in the command packet. When this bit This bit is used only in command chaining mode. It is onlyModified when the Dmac loads the control register from SNPDmac Local Bus Address Counter Table Address Counter Dmac VMEbus Address CounterDmac Byte Counter Dmac VMEbus Address CounterIrqs VMEbus Interrupter Control RegisterIrql IrqcVMEbus Interrupter Vector Register MPU Status and DMA Interrupt Count RegisterDmac Status Register Programming the Tick and Watchdog Timers VMEbus Arbiter Time-Out Control RegisterVgto Time onLbto VatoPrescaler Control Register Prescaler register = 256- Bclock MHzTick Timer 1 Compare Register Tick Timer 1 CounterTick timer 2 Counter Tick Timer 2 Compare RegisterTick Timer 2 Counter Board Control Register WDS/L Watchdog Timer Control RegisterWden Tick Timer 2 Control Register Tick Timer 1 Control Register Prescaler CounterProgramming the Local Bus Interrupter Local Bus Interrupter Summary Interrupt Vector Priority for Simultaneous InterruptsDmac Local Bus Interrupter Status Register bits SIG0 LM0LM1 SIG1SW2 SW0SW1 SW3VME3 VME1VME2 VME4Local Bus Interrupter Enable Register bits ESIG0 ELM0ELM1 ESIG1ESW2 ESW0ESW1 ESW3EIRQ3 EIRQ1EIRQ2 EIRQ4Software Interrupt Set Register bits Interrupt Clear Register bits Interrupt Level Register 1 bits IRQ1E Level Interrupt Level Register 2 bits These bits define the level of the tick timer 1 interruptThese bits define the level of the tick timer 2 interrupt SIG3 Level SIG2 Level Interrupt Level Register 3 bits SW5 Level SW4 Level These bits define the level of the VMEbus IRQ7 interrupt Interrupt Level Register 4 bitsVIRQ7 Level Spare LevelThese bits define the level of the VMEbus IRQ3 interrupt Interrupts may be mapped to any local bus interrupt levelVIRQ3 Level VIRQ4 LevelVBR VIRQ1 LevelVIRQ2 Level Control Register Connects to pin 18 of the Remote Status and Control Connects to pin 16 of the Remote Status and ControlConnects to pin 17 of the Remote Status and Control Not usedMiscellaneous Control Register EnintLcsr Programming Model Gcsr Programming Model 101 Programming the Gcsr VMEchip2 Revision Register 5shows a summary of the GcsrVMEchip2 Memory Map Gcsr Summary Offsets Bit Numbers LocaVMEchip2 ID Register VMEchip2 LM/SIG RegisterLM2 LM3RST VMEchip2 Board Status/Control RegisterISF General Purpose Register Local Bus $FFF40114/VMEbus $XXYA 16 bits Summary of Major Features PCCchip2PCCchip2 Block Diagram General DescriptionMPU Port and MPU Channel Attention Bbram Interface82596CA LAN Controller Interface Lanc Bus Error MC68040-Bus Master Support for 82596CALanc Interrupt 53C710 Scsi Controller Interface Parallel Port InterfaceGeneral Purpose I/O Pin CD2401 SCC InterfacePCCchip2 Tick Timer Address Range Selected Device Comments Overall Memory MapPCCchip2 Devices Memory Map Programming Model Summary of the PCCchip2 CSR is shown in TablePCCchip2 Memory Map Control and Status Registers Fast Chip ID Register Chip Revision RegisterGeneral Control Register FastVector Base Register DR0Interrupt Source IV3-IV0 Priority Gpio IRQProgramming the Tick Timers Tick Timer 2 Compare Register Prescaler Clock Adjust Register Prescaler Count RegisterPrescaler clock adjust register = 256 Bclk MHz CEN Clear On Compare. When this bit is high, the counter isWhen this bit is low, the counter is not reset $FFF42017 8 bits IEN General Purpose Input Interrupt Control RegisterIclr INTGPO Tick Timer 2 Interrupt Control RegisterGeneral Purpose Input/Output Pin Control Register GpoeCleared by writing a logic 1 into the Iclr control bit Interrupt Status. When this bit is high a Tick TimerInterrupt is being generated at the level programmed SCL R SCC Error Status and Interrupt Control RegistersSCC Error Status Register Writing a 1 to this bit clears bits 25 through 28 LTOIRQ SCC Modem Interrupt Control RegisterAvec SCC Transmit Interrupt Control Register SCC Receive Interrupt Control Register Modem Piack Register Transmit Piack Register Receive Piack Register Sclr Lanc Error Status and Interrupt Control RegistersLanc Error Status Register Writing a 1 to this bit clears bits 25 through 27 LTOInterrupt level for the 82596CA LANC. Level 0 does not Lanc qualified by the IEN bit. When this bit is high, a82596CA Lanc Interrupt Control Register This status bit reflects the state of the INT pin fromInterrupt level. Level 0 does not generate an interrupt Lanc Bus Error Interrupt Control RegisterSC0 pins, when the 82596CA Lanc performs IL2-IL0 if nonzeroProgramming the Scsi Error Status and Interrupt Registers Scsi Error Status RegisterScsi Interrupt Control Register Interrupt level for the Scsi Processor. Level 0 does notIL2-IL0 Programming the Printer PortPrinter ACK Interrupt Control Register When this bit is high, a printer Fault interrupt is being Printer Fault Interrupt Control RegisterFAULT. Level 0 does not generate an interrupt SEL. Level 0 does not generate an interrupt When this bit is high, a printer SEL interrupt is beingPrinter SEL Interrupt Control Register PE. Level 0 does not generate an interrupt When this bit is high, a printer PE interrupt is beingPrinter PE Interrupt Control Register BUSY. Level 0 does not generate an interrupt When this bit is high, a printer Busy interrupt is beingPrinter Busy Interrupt Control Register Printer Input Status Register STB Printer Port Control RegisterMAN Chip Speed Register INPDoen Printer Data Register Interrupt Priority Level Register Priority Level CommentsInterrupt Mask Level Register MSK2 MSK1 MSK0PCCchip2 Computer Group Literature Center Web Site Mcecc Functions Mcecc Functions on the Petra Asic FeaturesMcecc functions now implemented on the Petra chip include Performance Cache Coherency Memory System Cycle TimingCycle Types Error ReportingSingle Bit Error Cycle Type = Burst Read or Non-Burst Read Double Bit Error Cycle Type = Non-Burst Write Double Bit Error Cycle Type = Burst Read or Non-Burst ReadSingle Bit Error Cycle Type = Non-Burst Write Cycle Type = Burst WriteDouble Bit Error Cycle Type = Scrub Triple or Greater Bit Error Cycle Type = Non-Burst WriteSingle Bit Error Cycle Type = Scrub Triple or Greater Bit Error Cycle Type = ScrubRefresh Error LoggingScrub Chip Defaults ArbitrationProgramming Model Mcecc Sector Internal Register Memory Map Name D31 D30 D29 D28 D27 D26 D25 D24RWB7 RWB6 1st $FFF43000/2nd $FFF43100 8-bits Memory Size Memory Configuration RegisterMSIZ2-MSIZ0 Bit assignments for the Dram Control register are Base Address RegisterDram Control Register Bclk Frequency Register Unchanged by software or local reset Data Control RegisterMcecc Functions Scrub Control Register RWB0 RWB0 is a general-purpose read/write bitScrub Period Register Bits This register contains bits 7-0 of the Scrub Period registerSTOFF2-STOFF0 Chip Prescaler CounterScrub Time On/Time Off Register Scrubber Time On STON2-STON0Scrubber Time Off Scrub Prescaler Counter Bits Scrub Timer Counter Bits Scrub Address Counter Bits 1st $FFF43050/2nd $FFF43150 8-bits Error Logger Register Error Address Bits 1st $FFF43068/2nd $FFF43168 8-bits RSIZ2-RSIZ0 Error Syndrome RegisterDefaults Register SELI1, SELI0 Dram Array SizeRESST2-RESST0 Sdram Configuration Register SDCFG2-SDCFG0Initialization Programming Model Syndrome Decoding Syndrome Bit EncodingIdentifying Sdram Bank in Error ErrorMcecc Functions Computer Group Literature Center Web Site Table A-1. List of Changes Function Previous Implementation MVME1x2P2 ImplementationSummary of Changes Computer Group Literature Center Web Site Connection Diagrams Name NumberFigure B-1. MVME1X7P Printer Port with MVME712M Figure B-2. MVME1X7P Serial Port 1 Configured as DCE Figure B-3. MVME1X7P Serial Port 2 Configured as DCE Figure B-4. MVME1X7P Serial Port 3 Configured as DCE Figure B-5. MVME1X7P Serial Port 4 Configured as DCE Figure B-6. MVME1X7P Serial Port 1 Configured as DTE Figure B-7. MVME1X7P Serial Port 2 Configured as DTE Figure B-8. MVME1X7P Serial Port 3 Configured as DTE Figure B-9. MVME1X7P Serial Port 4 Configured as DTE Document Title Motorola Publication Number MCG DocumentsTable C-1. Motorola Computer Group Documents Document Title and Source Publication Number Manufacturers’ DocumentsTable C-2. Manufacturers’ Documents Publication Document Title and Source Number Related SpecificationsTable C-3. Related Specifications IEC 821 BUS Index Bbram 10,2-51 Gcsr IN-5 LAN IN-7 MVME1X7P IN-9 SCC Scsi IN-12 Enabling 2-32,2-35,2-43,2-44,2-50,2-51 Index