3

PCCchip2

Interrupt Priority Level Register

ADR/SIZ

 

 

 

$FFF4203E (8 bits)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

15

14

13

 

12

11

 

10

9

8

 

 

 

 

 

 

 

 

 

 

 

NAME

 

 

 

 

 

 

 

IPL2

IPL1

IPL0

 

 

 

 

 

 

 

 

 

 

 

OPER

R

R

R

 

R

R

 

R

R

R

 

 

 

 

 

 

 

 

 

 

 

RESET

0

0

0

 

0

0

 

X

X

X

 

 

 

 

 

 

 

 

 

 

 

IPL2-IPL0Interrupt Priority Level - These bits reflect the priority- encoded interrupt request level. This level is a combination of the PCCchip2 interrupt requests and the interrupt requests driven onto the EIPL2-EIPL0 pins.

Note that when the C040 bit is cleared, external devices can drive EIPL2-EIPL0 with their interrupt requests.

When C040 is set, the PCCchip2 drives EIPL2-EIPL0 with its interrupt requests. In this case (C040 set), IPL2- IPL0 only reflect PCCchip2 interrupt requests. The IPL bits are encoded as shown below:

IPL2

IPL1

IPL0

Priority Level

Comments

0

0

0

0

No Interrupt

0

0

1

1

Lowest Level

0

1

0

2

 

 

0

1

1

3

 

 

1

0

0

4

 

 

1

0

1

5

 

 

1

1

0

6

 

 

1

1

1

7

Highest Level

3-48

Computer Group Literature Center Web Site

Page 246
Image 246
Motorola MVME1X7P manual Interrupt Priority Level Register, Priority Level Comments