Motorola MVME1X7P manual Tick Timer 1 Control Register, Prescaler Counter

LCSR Programming Model

Tick Timer 1 Control Register

	ADR/SIZ					$FFF40060 (8 bits of 32)
	BIT	7	6		5		4	3	2	1	0
	NAME			OVF					COVF	COC	EN
	OPER			R					C	R/W	R/W
	RESET			0 PS					0 PS	0 PS	0 PS
		EN		When this bit is high, the counter increments. When this
				bit is low, the counter does not increment.
		COC		When this bit is high, the counter is reset to 0 when it
				compares with the compare register. When this bit is low,
				the counter is not reset.
		COVF		The overflow counter is cleared when a 1 is written to this
				bit.
		OVF		These bits are the output of the overflow counter. The
				overflow counter is incremented each time the tick timer
				sends an interrupt to the local bus interrupter. The
				overflow counter can be cleared by writing a 1 to the
				COVF bit.
Prescaler Counter
	ADR/SIZ					$FFF40064 (32 bits)
	BIT	31				. . .					0
	NAME						Prescaler Counter
	OPER						R/W
	RESET						0 P

The VMEchip2 has a 32-bit prescaler that provides the clocks required by the various timers in the chip. Access to the prescaler is provided for test purposes. The counter is described here because it may be useful in other applications. The lower 8 bits of the prescaler counter increment to $FF at the local bus clock rate and then they are loaded from the prescaler adjust register. When the load occurs, the upper 24 bits are incremented. When the prescaler adjust register is correctly programmed, the lower 8 bits increment at the local bus clock rate and the upper 24 bits increment every microsecond. The counter may be read at any time.

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http://www.motorola.com/computer/literature 2-73