Motorola MVME1X7P Lanc Error Status and Interrupt Control Registers, Lanc Error Status Register

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PCCchip2

LANC Error Status and Interrupt Control Registers

This section provides addresses and bit level descriptions of the LANC interrupt control registers and status register.

LANC Error Status Register

ADR/SIZ					$FFF42028 (8 bits)
BIT	31	30		29		28	27	26	25	24
NAME							PRTY	EXT	LTO	SCLR
OPER	R	R		R		R	R	R	R	W/R-0
RESET	0	0		0		0	0 PL	0 PL	0 PL	0
	SCLR		Writing a 1 to this bit clears bits 25 through 27 (LTO,
			EXT, and PRTY). Reading this bit always yields 0.

LTO,EXT,PRTY These bits indicate the status of the last Local Bus error condition encountered by the LANC while performing DMA accesses to the Local Bus.

A Local Bus error condition is flagged by the assertion of

TEA*.

When the LANC receives TEA*:

If the source of the error is local time-out, then LTO is set and EXT and PRTY are cleared.

If the source of the TEA* is due to an error in going to the VMEbus, then EXT is set and the other two status bits are cleared.

If the source of the error is DRAM parity check error, then PRTY is set and the other two status bits are cleared.

If the source of the error is none of the above conditions, then all three bits are cleared.

Writing a 1 to bit 24 (SCLR) also clears all three bits.

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