Motorola MVME1X7P manual Cache Coherency, Memory System Cycle Timing

4

MCECC Functions

Note The table is not complete because it cannot account for the effects of a write posting operation. If the Petra MCECC sector is idle and a write cycle is initiated on the local bus, the cycle is write- posted and the local bus is acknowleged in two clock ticks. If another bus cycle is initiated while the write post operation is in progress, the new cycle is stalled until the write posting is complete. The Read cycles are extended by one clock cycle if the the NCEBEN bit is set in the SDRAM Control register.

Since the bandwidth between the SDRAM and the processor local bus is generally higher than that of the logic it replaces (the MCECC pair and EDO DRAMs), software will take less time to execute. This could change the behavior of certain applications.

Table 4-2. Memory System Cycle Timing

Access		Memory States
Description
	Idle	Active Hit	Active Miss
Read Single	4 clock cycles	3 clock cycles	5 clock cycles
Read Burst	4-1-1-1 clock cycles	3-1-1-1 clock cycles	5-1-1-1 clock cycles
Write Burst	2-1-1-1 clock cycles	2-1-1-1 clock cycles	2-1-1-1 clock cycles
Write Longword	2 clock cycles	2 clock cycles	2 clock cycles
Write 1 or 2 Bytes	9 clock cycles	8 clock cycles	10 clock cycles

Cache Coherency

The MCECC sector supports the MC680x0 caching scheme on the local bus by always providing 32 bits of valid data during DRAM read cycles regardless of the number of bytes requested by the local bus master for the cycle. It also supports cache coherency by monitoring the memory inhibit (MI∗) signal.

For a write or read cycle, the MCECC sector always waits for MI∗ to be negated before it begins a read or write cycle to the DRAM. If another local bus slave asserts TA∗ or TEA∗ before MI∗ is negated, then the MCECC sector never begins the DRAM write cycle.

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