Drelm, Dfair, Dtbl, Den, Dhalt | Motorola MVME1X7P instruction

2

VMEchip2

always requests at the old level until it becomes bus master and the new level takes effect. If the VMEchip2 is bus master when the level is changed, the new level does not take effect until the bus has been released and re- requested at the old level. The requester always requests the VMEbus at level 3 the first time following a

SYSRESET.

	0	VMEbus request level 0
	1	VMEbus request level 1
	2	VMEbus request level 2
	3	VMEbus request level 3
DRELM	These bits define the VMEbus release mode for the
	DMAC requester. The DMAC always releases the bus
	when the FIFO is full (VMEbus to local bus) or empty
	(local bus to VMEbus).
	0	Release when the time on timer has expired
	1	and a BRx∗ signal is active on the VMEbus.
	1	Release when the time on timer has expired.
	2	Release when a BRx∗ signal is active on the
		VMEbus.
	3	Release when a BRx∗ signal is active on the
		VMEbus or the time on timer has expired.
DFAIR	When this bit is high, the DMAC requester operates in fair
	mode. It waits until its request level is inactive before
	requesting the VMEbus. When this bit is low, the DMAC
	requester does not operate in fair mode.
DTBL	The DMAC operates in direct mode when this bit is low,
	and it operates in command chaining mode when this bit
	is high.
DEN	The DMAC is enabled when this bit is set high. This bit
	always reads 0.
DHALT	When this bit is high, the DMAC halts at the end of a
	command when the DMAC is operating in command
	chaining mode. When this bit is low, the DMAC executes
	the next command in the list.

2-56	Computer Group Literature Center Web Site

Image 146

Motorola MVME1X7P manual Drelm, Dfair, Dtbl, Den, Dhalt

Contents

Programmer’s Reference Guide MVME1X7P Single-Board ComputerPage Safety Summary Flammability CE Notice European Community Limited and Restricted Rights Legend Contents Viii VMEchip2 Page Page PCCchip2 Xiii Chapter Appendix a Summary of Changes Xvi List of Figures Xviii List of Tables Page Model Number Characteristics About This Manual Overview of Contents Comments and Suggestions Conventions Used in This Manual CR represents the carriage return or Enter key Ctrl Xxv Xxvi Introduction Petra Asic and Second-Generation MVME1X7 Boards Programming Issues Feature FeaturesMVME1X7P Features Summary Block Diagram Applicable Industry Standards MVME167P Block Diagram MVME177P Block Diagram Programming Interfaces Data Bus Structure EEPROMs on the MVME1X7P Model Sockets Banks Flash Memory on the MVME177 MVME177 Sram Onboard Sdram Interfaces Battery-Backed-Up RAM and ClockVMEbus Interface Serial Port Interface Parallel Printer Interface Ethernet Interface Scsi Interface Programmable Tick TimersLocal Resources Functional Description Watchdog TimerLocal Bus Timeout Software-Programmable Hardware Interrupts Petra/VMEchip2 Redundant Logic VMEbus Interface and VMEchip2VMEchip2 General-Purpose I/O Functions Duplicated in VMEchip2 and Petra ASICs VMEchip2 Petra Chip Address Bit # Normal Address Range Memory MapsLocal Bus Memory Map Local Bus Memory Map Address Range Devices Accessed Port Size Local I/O Devices Memory Map 3KB Programming Issues Detailed I/O Memory Maps Tables 1-5 through 1-14 give the detailed memory maps for VMEchip2 Memory Map Sheet 1 Offset This sheet begins on facing VMEchip2 Memory Map Sheet 2 PRE Compare Register Counter Overflow VMEchip2 Memory Map Sheet 3 Offsets Bit Numbers Printer Memory Map PCCchip2 Memory Map SCC Transmit Piack Vector Base Register Register Bit Names Mcecc Internal Register Memory MapMcecc Base Address = $FFF43000 1st $FFF43100 2nd D31 D30 D29 D28 D27 D26 D25 D24 Register Register Bit Names Cirrus Logic CD2401 Serial Port Memory Map Option Registers Receive Interrupt Registers Channel Command and Status RegistersInterrupt Registers DMA Registers Transmit Interrupt RegistersModem Interrupt Registers DMA Receive Registers Timer Registers DMA Transmit Registers 10 CA Ethernet LAN Memory Map 11 C710 Scsi Memory Map BBRAM/TOD Clock Memory Map Address Range Description Size Bytes 13. Bbram Configuration Area Memory Map12. M48T58 BBRAM,TOD Clock Memory Map 14. TOD Clock Memory Map Address Data Bits Function MVME167P-24SE 01-W3620F35C Interrupt Acknowledge Map VMEbus Accesses to the Local BusVMEbus Memory Map VMEbus Short I/O Memory Map Example VMEchip2 Tick Timer 1 Periodic Interrupt Interrupt Handling To the Tick Timer 1 Compare Register description Cache Coherency MVME167P Cache Coherency MVME177P Using Bus Timers Instructions Indivisible Cycles15. Single-Cycle Instructions Supervisor Stack Pointer MC68060 VMEbus Access Timeout Sources of Local Bus ErrorsLocal Bus Timeout VMEbus Berr VMEchip2 Error ConditionsBus Error Processing MPU TEA Cause Unidentified MPU Parity ErrorMPU Offboard Error MPU Local Bus Time-out Dmac VMEbus ErrorDmac Parity Error Dmac Offboard Error Dmac LTO Error SCC Retry Error Dmac TEA Cause Unidentified SCC Parity Error SCC Offboard Error LAN Offboard Error SCC LTO ErrorLAN Parity Error Scsi Offboard Error LAN LTO ErrorScsi Parity Error Scsi LTO Error Programming Issues Computer Group Literature Center Web Site Features of the VMEchip2 Asic Function Features VMEchip2 Introduction Functional Blocks Local-Bus-to-VMEbus Interface VMEchip2 Block Diagram VMEchip2 Local-Bus-to-VMEbus Requester VMEchip2 VMEbus-to-Local-Bus Interface Functional Blocks Local-Bus-to-VMEbus DMA Controller Functional Blocks No-Address-Increment DMA Transfers Dmac VMEbus Requester Tick and Watchdog Timers Prescaler Tick Timers VMEbus Interrupter Arbiter Bus TimerVMEbus System Controller Iack Daisy-Chain Driver Dmac done Reset DriverLocal Bus Interrupter and Interrupt Handler VMEbus Sysfail interrupter Functional Blocks Lcsr Programming Model Global Control and Status Registers State of the bit following a reset, defined as follows 2shows a summary of the LCSRs VMEchip2 Memory Map-LCSR Summary Sheet 1 IO2 IO1 VMEchip2 Memory Map-LCSR Summary Sheet 2 IRQ7 IRQ6 IRQ5 Programming the VMEbus Slave Map Decoders Lcsr Programming Model VMEbus Slave Ending Address Register VMEbus Slave Starting Address Register Local-bus map decoder VMEbus Slave Address Translation Address Offset Register VMEbus Slave Address Translation Select Register Segment Address Translation Size Select Value $FFF4000C 16 bits SNP2 VMEbus Slave Write Post and Snoop Control RegisterWP2 PGM VMEbus Slave Address Modifier Select RegisterDAT BLK USR SUP WP1 SNP1 A24 access cycles When this bit is high, the first map decoder responds toBlock access cycles Cycles Programming the Local-Bus-to-VMEbus Map Decoders A32 access cyclesVMEbus supervisory access cycles. When this bit is low Bit is low, the first map decoder does not respond to VMEchip2 Local Bus Slave VMEbus Master Ending Address Register Local Bus Slave VMEbus Master Starting Address Register $FFF4001C 16 bits $FFF40024 16 bits Local Bus Slave VMEbus Master Attribute Register Segment defined by map decoder 3. When this bit is Decoder 3. Because the local-bus-to-VMEbus interface Not support block transfers, the block transfer address Segment defined by map decoder 2. When this bit isDecoder 2. Since the local-bus-to-VMEbus interface does Segment defined by map decoder 1. When this bit is Decoder 1. Because the local-bus-to-VMEbus interface VMEbus Slave Gcsr Group Address Register VMEbus Slave Gcsr Board Address Register EN2 Local-Bus-to-VMEbus Enable Control RegisterEN1 EN3 Local-Bus-to-VMEbus I/O Control Register I2EN Programming the VMEchip2 DMA ControllerI2WP ROM Control Register VMEchip2 Eprom Decoder, Sram and DMA Control Register Dmac Command Packet FormatDmac Registers Entry Function Tblsc ROM0 DWB LvrwdLvfair DHB Dtbl DrelmDfair DEN Linc Dmac Control Register 2 bitsTvme Vinc Control word in the command packet. When this bit This bit is used only in command chaining mode. It is onlyModified when the Dmac loads the control register from SNP Dmac Local Bus Address Counter Table Address Counter Dmac VMEbus Address CounterDmac Byte Counter Dmac VMEbus Address Counter Irqs VMEbus Interrupter Control RegisterIrql Irqc VMEbus Interrupter Vector Register MPU Status and DMA Interrupt Count Register Dmac Status Register Programming the Tick and Watchdog Timers VMEbus Arbiter Time-Out Control Register Vgto Time on Lbto Vato Prescaler Control Register Prescaler register = 256- Bclock MHz Tick Timer 1 Compare Register Tick Timer 1 Counter Tick timer 2 Counter Tick Timer 2 Compare RegisterTick Timer 2 Counter Board Control Register WDS/L Watchdog Timer Control RegisterWden Tick Timer 2 Control Register Tick Timer 1 Control Register Prescaler Counter Programming the Local Bus Interrupter Local Bus Interrupter Summary Interrupt Vector Priority for Simultaneous Interrupts Dmac Local Bus Interrupter Status Register bits SIG0 LM0LM1 SIG1 SW2 SW0SW1 SW3 VME3 VME1VME2 VME4 Local Bus Interrupter Enable Register bits ESIG0 ELM0ELM1 ESIG1 ESW2 ESW0ESW1 ESW3 EIRQ3 EIRQ1EIRQ2 EIRQ4 Software Interrupt Set Register bits Interrupt Clear Register bits Interrupt Level Register 1 bits IRQ1E Level Interrupt Level Register 2 bits These bits define the level of the tick timer 1 interruptThese bits define the level of the tick timer 2 interrupt SIG3 Level SIG2 Level Interrupt Level Register 3 bits SW5 Level SW4 Level These bits define the level of the VMEbus IRQ7 interrupt Interrupt Level Register 4 bitsVIRQ7 Level Spare Level These bits define the level of the VMEbus IRQ3 interrupt Interrupts may be mapped to any local bus interrupt levelVIRQ3 Level VIRQ4 Level VBR VIRQ1 LevelVIRQ2 Level Control Register Connects to pin 18 of the Remote Status and Control Connects to pin 16 of the Remote Status and ControlConnects to pin 17 of the Remote Status and Control Not used Miscellaneous Control Register Enint Lcsr Programming Model Gcsr Programming Model 101 Programming the Gcsr VMEchip2 Revision Register 5shows a summary of the GcsrVMEchip2 Memory Map Gcsr Summary Offsets Bit Numbers Loca VMEchip2 ID Register VMEchip2 LM/SIG Register LM2 LM3 RST VMEchip2 Board Status/Control RegisterISF General Purpose Register Local Bus $FFF40114/VMEbus $XXYA 16 bits Summary of Major Features PCCchip2 PCCchip2 Block Diagram General Description MPU Port and MPU Channel Attention Bbram Interface82596CA LAN Controller Interface Lanc Bus Error MC68040-Bus Master Support for 82596CA Lanc Interrupt 53C710 Scsi Controller Interface Parallel Port Interface General Purpose I/O Pin CD2401 SCC Interface PCCchip2 Tick Timer Address Range Selected Device Comments Overall Memory MapPCCchip2 Devices Memory Map Programming Model Summary of the PCCchip2 CSR is shown in Table PCCchip2 Memory Map Control and Status Registers Fast Chip ID Register Chip Revision Register General Control Register Fast Vector Base Register DR0 Interrupt Source IV3-IV0 Priority Gpio IRQ Programming the Tick Timers Tick Timer 2 Compare Register Prescaler Clock Adjust Register Prescaler Count Register Prescaler clock adjust register = 256 Bclk MHz CEN Clear On Compare. When this bit is high, the counter isWhen this bit is low, the counter is not reset $FFF42017 8 bits IEN General Purpose Input Interrupt Control RegisterIclr INT GPO Tick Timer 2 Interrupt Control RegisterGeneral Purpose Input/Output Pin Control Register Gpoe Cleared by writing a logic 1 into the Iclr control bit Interrupt Status. When this bit is high a Tick TimerInterrupt is being generated at the level programmed SCL R SCC Error Status and Interrupt Control RegistersSCC Error Status Register Writing a 1 to this bit clears bits 25 through 28 LTO IRQ SCC Modem Interrupt Control RegisterAvec SCC Transmit Interrupt Control Register SCC Receive Interrupt Control Register Modem Piack Register Transmit Piack Register Receive Piack Register Sclr Lanc Error Status and Interrupt Control RegistersLanc Error Status Register Writing a 1 to this bit clears bits 25 through 27 LTO Interrupt level for the 82596CA LANC. Level 0 does not Lanc qualified by the IEN bit. When this bit is high, a82596CA Lanc Interrupt Control Register This status bit reflects the state of the INT pin from Interrupt level. Level 0 does not generate an interrupt Lanc Bus Error Interrupt Control RegisterSC0 pins, when the 82596CA Lanc performs IL2-IL0 if nonzero Programming the Scsi Error Status and Interrupt Registers Scsi Error Status Register Scsi Interrupt Control Register Interrupt level for the Scsi Processor. Level 0 does not IL2-IL0 Programming the Printer PortPrinter ACK Interrupt Control Register When this bit is high, a printer Fault interrupt is being Printer Fault Interrupt Control RegisterFAULT. Level 0 does not generate an interrupt SEL. Level 0 does not generate an interrupt When this bit is high, a printer SEL interrupt is beingPrinter SEL Interrupt Control Register PE. Level 0 does not generate an interrupt When this bit is high, a printer PE interrupt is beingPrinter PE Interrupt Control Register BUSY. Level 0 does not generate an interrupt When this bit is high, a printer Busy interrupt is beingPrinter Busy Interrupt Control Register Printer Input Status Register STB Printer Port Control RegisterMAN Chip Speed Register INPDoen Printer Data Register Interrupt Priority Level Register Priority Level Comments Interrupt Mask Level Register MSK2 MSK1 MSK0 PCCchip2 Computer Group Literature Center Web Site Mcecc Functions Mcecc Functions on the Petra Asic FeaturesMcecc functions now implemented on the Petra chip include Performance Cache Coherency Memory System Cycle Timing Cycle Types Error ReportingSingle Bit Error Cycle Type = Burst Read or Non-Burst Read Double Bit Error Cycle Type = Non-Burst Write Double Bit Error Cycle Type = Burst Read or Non-Burst ReadSingle Bit Error Cycle Type = Non-Burst Write Cycle Type = Burst Write Double Bit Error Cycle Type = Scrub Triple or Greater Bit Error Cycle Type = Non-Burst WriteSingle Bit Error Cycle Type = Scrub Triple or Greater Bit Error Cycle Type = Scrub Refresh Error LoggingScrub Chip Defaults Arbitration Programming Model Mcecc Sector Internal Register Memory Map Name D31 D30 D29 D28 D27 D26 D25 D24 RWB7 RWB6 1st $FFF43000/2nd $FFF43100 8-bits Memory Size Memory Configuration RegisterMSIZ2-MSIZ0 Bit assignments for the Dram Control register are Base Address RegisterDram Control Register Bclk Frequency Register Unchanged by software or local reset Data Control Register Mcecc Functions Scrub Control Register RWB0 RWB0 is a general-purpose read/write bit Scrub Period Register Bits This register contains bits 7-0 of the Scrub Period register STOFF2-STOFF0 Chip Prescaler CounterScrub Time On/Time Off Register Scrubber Time On STON2-STON0Scrubber Time Off Scrub Prescaler Counter Bits Scrub Timer Counter Bits Scrub Address Counter Bits 1st $FFF43050/2nd $FFF43150 8-bits Error Logger Register Error Address Bits 1st $FFF43068/2nd $FFF43168 8-bits RSIZ2-RSIZ0 Error Syndrome RegisterDefaults Register SELI1, SELI0 Dram Array Size RESST2-RESST0 Sdram Configuration Register SDCFG2-SDCFG0 Initialization Programming Model Syndrome Decoding Syndrome Bit Encoding Identifying Sdram Bank in Error Error Mcecc Functions Computer Group Literature Center Web Site Table A-1. List of Changes Function Previous Implementation MVME1x2P2 Implementation Summary of Changes Computer Group Literature Center Web Site Connection Diagrams Name Number Figure B-1. MVME1X7P Printer Port with MVME712M Figure B-2. MVME1X7P Serial Port 1 Configured as DCE Figure B-3. MVME1X7P Serial Port 2 Configured as DCE Figure B-4. MVME1X7P Serial Port 3 Configured as DCE Figure B-5. MVME1X7P Serial Port 4 Configured as DCE Figure B-6. MVME1X7P Serial Port 1 Configured as DTE Figure B-7. MVME1X7P Serial Port 2 Configured as DTE Figure B-8. MVME1X7P Serial Port 3 Configured as DTE Figure B-9. MVME1X7P Serial Port 4 Configured as DTE Document Title Motorola Publication Number MCG DocumentsTable C-1. Motorola Computer Group Documents Document Title and Source Publication Number Manufacturers’ DocumentsTable C-2. Manufacturers’ Documents Publication Document Title and Source Number Related SpecificationsTable C-3. Related Specifications IEC 821 BUS Index Bbram 10,2-51 Gcsr IN-5 LAN IN-7 MVME1X7P IN-9 SCC Scsi IN-12 Enabling 2-32,2-35,2-43,2-44,2-50,2-51 Index