SCC Receive Interrupt Control Register | Motorola MVME1X7P specs

3

PCCchip2

SCC Receive Interrupt Control Register

ADR/SIZ

$FFF4201F (8 bits)

BIT

7

6

5

4

3

2

1

0

NAME

SC1

SC0

IRQ

IEN

AVEC

IL2

IL1

IL0

OPER

R/W

R/W

R

R/W

R/W

R/W

R/W

R/W

RESET

0 PL

0 PL

X

0 PL

0 PL

0 PL

0 PL

0 PL

IL2-IL0

Interrupt Request Level. These three bits select the

interrupt level for SCC Receive Interrupt. Level 0 does

not generate an interrupt.

AVEC

When this bit is high, the PCCchip2 supplies the interrupt

vector to the MPU during an IACK for SCC receive

interrupt. When this bit is low, the PCCchip2 obtains the

vector from the SCC and passes it to the MPU. The use of

the AVEC mode is not recommended.

IEN

Interrupt Enable. When this bit is high, the interrupt is

enabled. The interrupt is disabled when this bit is low.

IRQ

Interrupt Status. This status bit reflects the state of the

SCC-IRQ3 pin of the CD2401 (qualified by the IEN bit).

When this bit is high, an SCC receive interrupt is being

generated at the level programmed in IL2-IL0 (if

nonzero). This status bit does not need to be cleared,

because it is not edge-sensitive.

SC1-SC0

Snoop Control. These control bits determine the value that

the PCCchip2 drives onto the local MC68040 bus SC1

and SC0 pins, when the CL-CD2401(SCC) performs

DMA accesses. During SCC DMA, when bit SC0 is 0,

Local Bus pin SC0 is low, and when bit SC0 is 1, pin SC0

is high. The same relationship holds true for bit and pin

SC1. See the M68040 and MC68060 user’s manuals for

details on how it uses the Snoop Control signals.

Note On the MVME177P, which uses only SC1, the SC0 bit must be 0.

3-30	Computer Group Literature Center Web Site

Image 228

Motorola MVME1X7P manual SCC Receive Interrupt Control Register

Contents

Programmer’s Reference Guide MVME1X7P Single-Board ComputerPage Safety Summary Flammability CE Notice European Community Limited and Restricted Rights Legend Contents Viii VMEchip2 Page Page PCCchip2 Xiii Chapter Appendix a Summary of Changes Xvi List of Figures Xviii List of Tables Page Model Number Characteristics About This Manual Overview of Contents Comments and Suggestions Conventions Used in This Manual CR represents the carriage return or Enter key Ctrl Xxv Xxvi Introduction Petra Asic and Second-Generation MVME1X7 Boards Programming Issues Features MVME1X7P Features SummaryFeature Block Diagram Applicable Industry Standards MVME167P Block Diagram MVME177P Block Diagram Programming Interfaces Data Bus Structure EEPROMs on the MVME1X7P Model Sockets Banks Flash Memory on the MVME177 MVME177 Sram Onboard Sdram Battery-Backed-Up RAM and Clock VMEbus InterfaceInterfaces Serial Port Interface Parallel Printer Interface Ethernet Interface Programmable Tick Timers Local ResourcesScsi Interface Watchdog Timer Local Bus TimeoutFunctional Description Software-Programmable Hardware Interrupts VMEbus Interface and VMEchip2 VMEchip2 General-Purpose I/OPetra/VMEchip2 Redundant Logic Functions Duplicated in VMEchip2 and Petra ASICs VMEchip2 Petra Chip Address Bit # Memory Maps Local Bus Memory MapNormal Address Range Local Bus Memory Map Address Range Devices Accessed Port Size Local I/O Devices Memory Map 3KB Programming Issues Detailed I/O Memory Maps Tables 1-5 through 1-14 give the detailed memory maps for VMEchip2 Memory Map Sheet 1 Offset This sheet begins on facing VMEchip2 Memory Map Sheet 2 PRE Compare Register Counter Overflow VMEchip2 Memory Map Sheet 3 Offsets Bit Numbers Printer Memory Map PCCchip2 Memory Map SCC Transmit Piack Vector Base Register Mcecc Internal Register Memory Map Mcecc Base Address = $FFF43000 1st $FFF43100 2ndRegister Bit Names D31 D30 D29 D28 D27 D26 D25 D24 Register Register Bit Names Cirrus Logic CD2401 Serial Port Memory Map Option Registers Channel Command and Status Registers Interrupt RegistersReceive Interrupt Registers Transmit Interrupt Registers Modem Interrupt RegistersDMA Registers DMA Receive Registers Timer Registers DMA Transmit Registers 10 CA Ethernet LAN Memory Map 11 C710 Scsi Memory Map BBRAM/TOD Clock Memory Map 13. Bbram Configuration Area Memory Map 12. M48T58 BBRAM,TOD Clock Memory MapAddress Range Description Size Bytes 14. TOD Clock Memory Map Address Data Bits Function MVME167P-24SE 01-W3620F35C VMEbus Accesses to the Local Bus VMEbus Memory MapInterrupt Acknowledge Map VMEbus Short I/O Memory Map Example VMEchip2 Tick Timer 1 Periodic Interrupt Interrupt Handling To the Tick Timer 1 Compare Register description Cache Coherency MVME167P Cache Coherency MVME177P Using Bus Timers Indivisible Cycles 15. Single-Cycle InstructionsInstructions Supervisor Stack Pointer MC68060 Sources of Local Bus Errors Local Bus TimeoutVMEbus Access Timeout VMEbus Berr Error Conditions Bus Error ProcessingVMEchip2 MPU Parity Error MPU Offboard ErrorMPU TEA Cause Unidentified Dmac VMEbus Error Dmac Parity ErrorMPU Local Bus Time-out Dmac Offboard Error Dmac LTO Error SCC Retry Error Dmac TEA Cause Unidentified SCC Parity Error SCC Offboard Error SCC LTO Error LAN Parity ErrorLAN Offboard Error LAN LTO Error Scsi Parity ErrorScsi Offboard Error Scsi LTO Error Programming Issues Computer Group Literature Center Web Site Features of the VMEchip2 Asic Function Features VMEchip2 Introduction Functional Blocks Local-Bus-to-VMEbus Interface VMEchip2 Block Diagram VMEchip2 Local-Bus-to-VMEbus Requester VMEchip2 VMEbus-to-Local-Bus Interface Functional Blocks Local-Bus-to-VMEbus DMA Controller Functional Blocks No-Address-Increment DMA Transfers Dmac VMEbus Requester Tick and Watchdog Timers Prescaler Tick Timers VMEbus Interrupter Bus Timer VMEbus System ControllerArbiter Iack Daisy-Chain Driver Reset Driver Local Bus Interrupter and Interrupt HandlerDmac done VMEbus Sysfail interrupter Functional Blocks Lcsr Programming Model Global Control and Status Registers State of the bit following a reset, defined as follows 2shows a summary of the LCSRs VMEchip2 Memory Map-LCSR Summary Sheet 1 IO2 IO1 VMEchip2 Memory Map-LCSR Summary Sheet 2 IRQ7 IRQ6 IRQ5 Programming the VMEbus Slave Map Decoders Lcsr Programming Model VMEbus Slave Ending Address Register VMEbus Slave Starting Address Register Local-bus map decoder VMEbus Slave Address Translation Address Offset Register VMEbus Slave Address Translation Select Register Segment Address Translation Size Select Value $FFF4000C 16 bits VMEbus Slave Write Post and Snoop Control Register WP2SNP2 VMEbus Slave Address Modifier Select Register DATPGM BLK USR SUP WP1 SNP1 When this bit is high, the first map decoder responds to Block access cyclesA24 access cycles Cycles A32 access cycles VMEbus supervisory access cycles. When this bit is lowProgramming the Local-Bus-to-VMEbus Map Decoders Bit is low, the first map decoder does not respond to VMEchip2 Local Bus Slave VMEbus Master Ending Address Register Local Bus Slave VMEbus Master Starting Address Register $FFF4001C 16 bits $FFF40024 16 bits Local Bus Slave VMEbus Master Attribute Register Segment defined by map decoder 3. When this bit is Decoder 3. Because the local-bus-to-VMEbus interface Segment defined by map decoder 2. When this bit is Decoder 2. Since the local-bus-to-VMEbus interface doesNot support block transfers, the block transfer address Segment defined by map decoder 1. When this bit is Decoder 1. Because the local-bus-to-VMEbus interface VMEbus Slave Gcsr Group Address Register VMEbus Slave Gcsr Board Address Register Local-Bus-to-VMEbus Enable Control Register EN1EN2 EN3 Local-Bus-to-VMEbus I/O Control Register Programming the VMEchip2 DMA Controller I2WPI2EN ROM Control Register VMEchip2 Dmac Command Packet Format Dmac RegistersEprom Decoder, Sram and DMA Control Register Entry Function Tblsc ROM0 Lvrwd LvfairDWB DHB Drelm DfairDtbl DEN Dmac Control Register 2 bits TvmeLinc Vinc This bit is used only in command chaining mode. It is only Modified when the Dmac loads the control register fromControl word in the command packet. When this bit SNP Dmac Local Bus Address Counter Dmac VMEbus Address Counter Dmac Byte CounterTable Address Counter Dmac VMEbus Address Counter VMEbus Interrupter Control Register IrqlIrqs Irqc VMEbus Interrupter Vector Register MPU Status and DMA Interrupt Count Register Dmac Status Register Programming the Tick and Watchdog Timers VMEbus Arbiter Time-Out Control Register Vgto Time on Lbto Vato Prescaler Control Register Prescaler register = 256- Bclock MHz Tick Timer 1 Compare Register Tick Timer 1 Counter Tick Timer 2 Compare Register Tick Timer 2 CounterTick timer 2 Counter Board Control Register Watchdog Timer Control Register WdenWDS/L Tick Timer 2 Control Register Tick Timer 1 Control Register Prescaler Counter Programming the Local Bus Interrupter Local Bus Interrupter Summary Interrupt Vector Priority for Simultaneous Interrupts Dmac Local Bus Interrupter Status Register bits LM0 LM1SIG0 SIG1 SW0 SW1SW2 SW3 VME1 VME2VME3 VME4 Local Bus Interrupter Enable Register bits ELM0 ELM1ESIG0 ESIG1 ESW0 ESW1ESW2 ESW3 EIRQ1 EIRQ2EIRQ3 EIRQ4 Software Interrupt Set Register bits Interrupt Clear Register bits Interrupt Level Register 1 bits IRQ1E Level These bits define the level of the tick timer 1 interrupt These bits define the level of the tick timer 2 interruptInterrupt Level Register 2 bits SIG3 Level SIG2 Level Interrupt Level Register 3 bits SW5 Level SW4 Level Interrupt Level Register 4 bits VIRQ7 LevelThese bits define the level of the VMEbus IRQ7 interrupt Spare Level Interrupts may be mapped to any local bus interrupt level VIRQ3 LevelThese bits define the level of the VMEbus IRQ3 interrupt VIRQ4 Level VIRQ1 Level VIRQ2 LevelVBR Control Register Connects to pin 16 of the Remote Status and Control Connects to pin 17 of the Remote Status and ControlConnects to pin 18 of the Remote Status and Control Not used Miscellaneous Control Register Enint Lcsr Programming Model Gcsr Programming Model 101 Programming the Gcsr 5shows a summary of the Gcsr VMEchip2 Memory Map Gcsr SummaryVMEchip2 Revision Register Offsets Bit Numbers Loca VMEchip2 ID Register VMEchip2 LM/SIG Register LM2 LM3 VMEchip2 Board Status/Control Register ISFRST General Purpose Register Local Bus $FFF40114/VMEbus $XXYA 16 bits Summary of Major Features PCCchip2 PCCchip2 Block Diagram General Description Bbram Interface 82596CA LAN Controller InterfaceMPU Port and MPU Channel Attention Lanc Bus Error MC68040-Bus Master Support for 82596CA Lanc Interrupt 53C710 Scsi Controller Interface Parallel Port Interface General Purpose I/O Pin CD2401 SCC Interface PCCchip2 Tick Timer Overall Memory Map PCCchip2 Devices Memory MapAddress Range Selected Device Comments Programming Model Summary of the PCCchip2 CSR is shown in Table PCCchip2 Memory Map Control and Status Registers Fast Chip ID Register Chip Revision Register General Control Register Fast Vector Base Register DR0 Interrupt Source IV3-IV0 Priority Gpio IRQ Programming the Tick Timers Tick Timer 2 Compare Register Prescaler Clock Adjust Register Prescaler Count Register Prescaler clock adjust register = 256 Bclk MHz Clear On Compare. When this bit is high, the counter is When this bit is low, the counter is not resetCEN $FFF42017 8 bits General Purpose Input Interrupt Control Register IclrIEN INT Tick Timer 2 Interrupt Control Register General Purpose Input/Output Pin Control RegisterGPO Gpoe Interrupt Status. When this bit is high a Tick Timer Interrupt is being generated at the level programmedCleared by writing a logic 1 into the Iclr control bit SCC Error Status and Interrupt Control Registers SCC Error Status RegisterSCL R Writing a 1 to this bit clears bits 25 through 28 LTO SCC Modem Interrupt Control Register AvecIRQ SCC Transmit Interrupt Control Register SCC Receive Interrupt Control Register Modem Piack Register Transmit Piack Register Receive Piack Register Lanc Error Status and Interrupt Control Registers Lanc Error Status RegisterSclr Writing a 1 to this bit clears bits 25 through 27 LTO Lanc qualified by the IEN bit. When this bit is high, a 82596CA Lanc Interrupt Control RegisterInterrupt level for the 82596CA LANC. Level 0 does not This status bit reflects the state of the INT pin from Lanc Bus Error Interrupt Control Register SC0 pins, when the 82596CA Lanc performsInterrupt level. Level 0 does not generate an interrupt IL2-IL0 if nonzero Programming the Scsi Error Status and Interrupt Registers Scsi Error Status Register Scsi Interrupt Control Register Interrupt level for the Scsi Processor. Level 0 does not Programming the Printer Port Printer ACK Interrupt Control RegisterIL2-IL0 Printer Fault Interrupt Control Register FAULT. Level 0 does not generate an interruptWhen this bit is high, a printer Fault interrupt is being When this bit is high, a printer SEL interrupt is being Printer SEL Interrupt Control RegisterSEL. Level 0 does not generate an interrupt When this bit is high, a printer PE interrupt is being Printer PE Interrupt Control RegisterPE. Level 0 does not generate an interrupt When this bit is high, a printer Busy interrupt is being Printer Busy Interrupt Control RegisterBUSY. Level 0 does not generate an interrupt Printer Input Status Register Printer Port Control Register MANSTB INP DoenChip Speed Register Printer Data Register Interrupt Priority Level Register Priority Level Comments Interrupt Mask Level Register MSK2 MSK1 MSK0 PCCchip2 Computer Group Literature Center Web Site Mcecc Functions Features Mcecc functions now implemented on the Petra chip includeMcecc Functions on the Petra Asic Performance Cache Coherency Memory System Cycle Timing Error Reporting Single Bit Error Cycle Type = Burst Read or Non-Burst ReadCycle Types Double Bit Error Cycle Type = Burst Read or Non-Burst Read Single Bit Error Cycle Type = Non-Burst WriteDouble Bit Error Cycle Type = Non-Burst Write Cycle Type = Burst Write Triple or Greater Bit Error Cycle Type = Non-Burst Write Single Bit Error Cycle Type = ScrubDouble Bit Error Cycle Type = Scrub Triple or Greater Bit Error Cycle Type = Scrub Error Logging ScrubRefresh Chip Defaults Arbitration Programming Model Mcecc Sector Internal Register Memory Map Name D31 D30 D29 D28 D27 D26 D25 D24 RWB7 RWB6 1st $FFF43000/2nd $FFF43100 8-bits Memory Configuration Register MSIZ2-MSIZ0Memory Size Base Address Register Dram Control RegisterBit assignments for the Dram Control register are Bclk Frequency Register Unchanged by software or local reset Data Control Register Mcecc Functions Scrub Control Register RWB0 RWB0 is a general-purpose read/write bit Scrub Period Register Bits This register contains bits 7-0 of the Scrub Period register Chip Prescaler Counter Scrub Time On/Time Off RegisterSTOFF2-STOFF0 STON2-STON0 Scrubber Time OffScrubber Time On Scrub Prescaler Counter Bits Scrub Timer Counter Bits Scrub Address Counter Bits 1st $FFF43050/2nd $FFF43150 8-bits Error Logger Register Error Address Bits 1st $FFF43068/2nd $FFF43168 8-bits Error Syndrome Register Defaults RegisterRSIZ2-RSIZ0 SELI1, SELI0 Dram Array Size RESST2-RESST0 Sdram Configuration Register SDCFG2-SDCFG0 Initialization Programming Model Syndrome Decoding Syndrome Bit Encoding Identifying Sdram Bank in Error Error Mcecc Functions Computer Group Literature Center Web Site Table A-1. List of Changes Function Previous Implementation MVME1x2P2 Implementation Summary of Changes Computer Group Literature Center Web Site Connection Diagrams Name Number Figure B-1. MVME1X7P Printer Port with MVME712M Figure B-2. MVME1X7P Serial Port 1 Configured as DCE Figure B-3. MVME1X7P Serial Port 2 Configured as DCE Figure B-4. MVME1X7P Serial Port 3 Configured as DCE Figure B-5. MVME1X7P Serial Port 4 Configured as DCE Figure B-6. MVME1X7P Serial Port 1 Configured as DTE Figure B-7. MVME1X7P Serial Port 2 Configured as DTE Figure B-8. MVME1X7P Serial Port 3 Configured as DTE Figure B-9. MVME1X7P Serial Port 4 Configured as DTE MCG Documents Table C-1. Motorola Computer Group DocumentsDocument Title Motorola Publication Number Manufacturers’ Documents Table C-2. Manufacturers’ DocumentsDocument Title and Source Publication Number Related Specifications Table C-3. Related SpecificationsPublication Document Title and Source Number IEC 821 BUS Index Bbram 10,2-51 Gcsr IN-5 LAN IN-7 MVME1X7P IN-9 SCC Scsi IN-12 Enabling 2-32,2-35,2-43,2-44,2-50,2-51 Index