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Signal Connections for In-System Programming and Debugging

VCC

 

J1 (SEE NOTE A)

 

 

 

J2 (SEE NOTE A)

 

 

 

 

 

R1

C2

C3

 

 

 

10 µF

0.1 µF

 

 

 

47 KΩ

 

 

 

 

 

 

 

 

(SEE NOTE B)

 

 

 

 

JTAG

 

 

 

VCC TOOL

2

1

TDO/TDI

 

 

 

 

 

 

VCC TARGET

4

3

TDI/VPP

 

 

 

 

 

 

 

6

5

TMS

 

 

 

 

 

 

TEST/VPP

8

7

TCK

 

 

 

 

 

 

 

10

9

GND

 

 

 

 

 

 

 

12

11

RST (SEE NOTE D)

 

 

 

 

 

 

 

14

13

 

 

 

 

 

 

C1

 

 

 

 

 

10 NF/2.2 NF

 

 

 

 

(SEE NOTES B AND E)

 

 

VCC/AVCC/DVCC

MSP430FXXX

RST/NMI

TDO/TDI

TDI/VPP

TMS

TCK

TEST/VPP (SEE NOTE C)

VSS/AVSS/DVSS

AMake either connection J1 in case a local target power supply is used or connection J2 to power target from the debug/programming adapter.

BThe RST/NMI pin R1/C1 configuration is device family dependent. See the respective MSP430 family user'sguide for the recommended configuration.

CThe TEST pin is available only on MSP430 family members with multiplexed JTAG pins. See the device-specific data sheet to determine if this pin is available.

DThe connection to the JTAG connector RST pin is optional when using 4-wire JTAG communication mode capable-only devices and not required for device programming or debugging. However, this connection is required when using 2-wire JTAG communication mode capable devices in 4-wire JTAG mode.

EWhen using 2-wire JTAG communication capable devices in 4-wire JTAG mode, the upper limit for C1 should not exceed 2.2 nF. This applies to both TI FET interface modules (LPT/USB FET).

Figure 2-1. Signal Connections for 4-Wire JTAG Communication

SLAU278F –May 2009 –Revised December 2010

Design Considerations for In-Circuit Programming

25

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Texas Instruments MSP430 manual 10 µF 47 KΩ, 10 NF/2.2 NF