Linear BPI Flash, Pin Number Pin Name | Xilinx SP605 specs

Chapter 1: SP605 Evaluation Board

4. Linear BPI Flash

A Numonyx JS28F256P30 Linear Flash memory (U25) on the SP605 (Figure 1-5) provides 32 MB of non-volatile storage that can be used for configuration as well as software storage. The Linear Flash is operated in asynchronous mode.

For details on configuring the FPGA, see “Configuration Options.”

U1

U25

FPGA

BPI Flash

Interface

ADDR, DATA, CTRL

Numonyx Type P30

JS28F256P30

			UG526_05_092409
		Figure 1-5:Linear BPI Flash Interface
	Table 1-7:Linear Flash Connections

	U1 FPGA Pin	Schematic Net Name	U25 BPI FLASH

			Pin Number		Pin Name
			Pin Number		Pin Name

	N22	FLASH_A0	29		A1

	N20	FLASH_A1	25		A2

	M22	FLASH_A2	24		A3

	M21	FLASH_A3	23		A4

	L19	FLASH_A4	22		A5

	K20	FLASH_A5	21		A6

	H22	FLASH_A6	20		A7

	H21	FLASH_A7	19		A8

	L17	FLASH_A8	8		A9

	K17	FLASH_A9	7		A10

	G22	FLASH_A10	6		A11

	G20	FLASH_A11	5		A12

	K18	FLASH_A12	4		A13

	K19	FLASH_A13	3		A14

	H20	FLASH_A14	2		A15

	J19	FLASH_A15	1		A16


18		www.xilinx.com	SP605 Hardware User Guide
			UG526 (v1.1.1) February 1, 2010

Image 18

Xilinx SP605 manual Linear BPI Flash, Pin Number Pin Name

Contents

SP605 Hardware User Guide UG526 v1.1.1 February 1, 2010 optional Revision History Date Version Revision Table of Contents SP605 Hardware User Guide About This Guide Additional Support Resources Preface About This Guide SP605 Evaluation Board Additional Information Features SP605 Evaluation Board Block Diagram Overview SP605 Features Feature Detailed Description SP605 Features Cont’d Configuration SP605 Evaluation Board SP605 Features Cont’dSpartan-6 XC6SLX45T-3FGG484 Fpga Detailed Description MB DDR3 Component MemoryVoltage Rails 2I/O Voltage Rail of Fpga Banks Schematic Net Name Memory U42 Pin Pin Number Pin Name 5DDR3 Component Memory Connections U1 Fpga SPI x4 Flash 3J17 SPI Flash Programming Header Schematic Net Name Detailed Description 6SPI x4 Memory Connections Linear BPI Flash Pin Number Pin Name FLASHA16 System ACE CF and CompactFlash Connector Fpga Design Considerations for the Configuration Flash 8System ACE CF Connections U1 Fpga Pin Schematic Net Name1 U17 XCCACETQ144I USB Jtag Clock Generation Oscillator Differential Oscillator Socket Single-Ended, 2.5V or 8SP605 X2 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential Multi-Gigabit Transceivers GTP MGTs MGT Refclk Smarefclkn 11PCIe Edge Connector Connections U1 Fpga Pin P4 PCIe Edge ConnectorPCI Express Endpoint Connectivity References SFP Module Connector Sfpclkqop Bit2 Bit1 Bit0 14PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY 15Ethernet PHY Connections U1 Fpga Pin PHYRXD7 USB-to-UART Bridge 17 USB-to-UART Connections DVI Codec IIC Bus 11IIC Bus Topology Kb NV Memory Iicsclsfp Iicsdamain SDA Signal Name Color Label Description Status LEDs Ethernet PHY Status LEDs 13Ethernet PHY Status LEDs Fpga Init and Done LEDs 22 Fpga Init and Done LED Connections 23User LED Connections U1 Fpga Pin User I/OUser LEDs Controlled LED User Pushbutton Switches SW6 User DIP Switch User SIP Header U1 Fpga Pin User SMA Gpio Usersmagpion Usersmagpiop Switches Power On/Off Slide Switch SW2 Sysaceresetb Pushbutton SW9 Active-Low Fpgaprogb Pushbutton SW3 Active-Low 23System ACE CF CompactFlash Image Select DIP Switch S1 Mode DIP Switch SW1 Active-High 24FPGA Mode DIP Switch SW1 Vita 57.1 FMC LPC Connector 28VITA 57.1 FMC LPC Connections LPC Pin Power Management AC Adapter and 12V Input Power Jack/Switch Onboard Power Regulation Power Management UCD9240PFC Configuration Options 30SP605 Fpga Configuration Modes M10 Bus WidthConfiguration Solution User Guide Section SP605 Evaluation Board Table A-1Default Switch Settings Function/Type Default FMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF Appendix C SP605 Master UCF NET Fmcpwrgoodflashrstb NET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References