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manual UG526 v1.1.1 February 1, 2010 optional, SP605 Hardware User Guide
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SP605
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Block Diagram
Onboard Power Regulation Configuration Options
SYSACERESETB Pushbutton SW9 Active-Low
Default Jumper and Switch Settings
Signal Name
Direction Indicator DUP TX RX
Power Management
Updated -17 and Figure
External Access
System ACE CF and CompactFlash Connector 6. USB JTAG
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SP605 Hardware User Guide
[Guide Subtitle] [optional]
UG526 (v1.1.1) February 1, 2010 [optional]
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Contents
SP605 Hardware User Guide
UG526 v1.1.1 February 1, 2010 optional
Guide Subtitle optional
Revision History
Updated Figure 1-17 and Figure
Date
Version
Preface About This Guide
Table of Contents
Chapter 1 SP605 Evaluation Board
Appendix B VITA 57.1 FMC LPC Connector Pinout
Appendix A Default Jumper and Switch Settings
Appendix C SP605 Master UCF Appendix D References
Mode DIP Switch SW1 Active-High 18. VITA 57.1 FMC LPC Connector
Appendix A, “Default Jumper and Switch Settings.”
Guide Contents
Appendix B, “VITA 57.1 FMC LPC Connector Pinout.”
About This Guide
Preface About This Guide
Additional Support Resources
Chapter
SP605 Evaluation Board
Overview
Additional Information
5. System ACE CF and CompactFlash Connector 6. USB JTAG
Features
10. SFP Module Connector 11. 10/100/1000 Tri-Speed Ethernet PHY
Chapter 1 SP605 Evaluation Board
17. Switches
Block Diagram
18. VITA 57.1 FMC LPC Connector Configuration Options
4. Linear BPI Flash 5. System ACE CF and CompactFlash Connector
Feature
SP605 Features
Related Xilinx Documents
Detailed Description
Detailed Description
SP605 Features Cont’d
Feature
Linear BPI Flash
1. Spartan-6 XC6SLX45T-3FGG484 FPGA
Configuration
References
SP605 Features Cont’d
2. 128 MB DDR3 Component Memory
Signal Name
I/O Voltage Rails
Table 1-2 I/O Voltage Rail of FPGA Banks
Table 1-4 FPGA On-Chip OCT Termination External Resistor Requirements
Schematic Net Name
U1 FPGA Pin
FPGA Pin Number
References
DDR3 Component Memory Connections Cont’d
Detailed Description
Memory U42
Silkscreen
3. SPI x4 Flash
Figure 1-3 J17 SPI Flash Programming Header
Figure 1-4 SPI Flash Interface Topology
SPI MEM U32
Detailed Description Table 1-6 SPI x4 Memory Connections
SPI HDR J17
Schematic Net Name
Figure 1-5 Linear BPI Flash Interface
4. Linear BPI Flash
Table 1-7 Linear Flash Connections
U25 BPI FLASH
Schematic Net Name
Detailed Description Table 1-7 Linear Flash Connections Cont’d
U1 FPGA Pin
U25 BPI FLASH
FPGA Design Considerations for the Configuration Flash
5. System ACE CF and CompactFlash Connector
References
Chapter 1 SP605 Evaluation Board
Table 1-8 System ACE CF Connections
Schematic Net Name1
U17 XCCACETQ144I
Detailed Description
6. USB JTAG
Figure 1-6 JTAG Chain Diagram
Table 1-8 System ACE CF Connections Cont’d
Schematic Net Name
Oscillator Differential
7. Clock Generation
Figure 1-7 VITA 57.1 FMC LPC J2 JTAG Bypass Jumper J19
References
Figure 1-8 SP605 X2 Oscillator Socket Pin 1 Location Identifiers
Oscillator Socket Single-Ended, 2.5V or
Figure 1-9 SP605 X2 Oscillator Pin 1 Location Identifiers
Silkscreened outline has beveled corner Socket has notch in crossbar
8. Multi-Gigabit Transceivers GTP MGTs
SMA Connectors Differential
Table 1-9 SP605 Clock Source Connections
Source
SMA MGT Connectors
Figure 1-10 GTP SMA Clock
MGT REFCLK
Chapter 1 SP605 Evaluation Board
SMA Pin
Detailed Description Table 1-10 GTP SMA Clock Connections
Schematic Net Name
U1 FPGA Pin
P4 PCIe Edge Connector
Table 1-11 PCIe Edge Connector Connections
9. PCI Express Endpoint Connectivity
Chapter 1 SP605 Evaluation Board
Detailed Description
References
Product information
SFP Control/Status Signal
10. SFP Module Connector
P2 SFP Module Connector
Table 1-12 SFP Module Control and Status
11. 10/100/1000 Tri-Speed Ethernet PHY
Table 1-14 PHY Configuration Pins
Bit2
Bit1
References
Table 1-15 Ethernet PHY Connections Cont’d
Chapter 1 SP605 Evaluation Board
U1 FPGA Pin
USB Connector
Table 1-16 USB Type B Pin Assignments and Signal Definitions
12. USB-to-UART Bridge
Description
13. DVI CODEC
Schematic Net
Table 1-18 DVI Controller Connections
U31 Chrontel CH7301C
Figure 1-11 IIC Bus Topology
14. IIC Bus
Detailed Description
External Access
Schematic
8-Kb NV Memory
Table 1-19 IIC Bus Connections
Detailed Description Table 1-20 IIC Memory Connections
Schematic Netname
IIC Memory U4
References
Table 1-21 Status LEDs
15. Status LEDs
Color
Label
Ethernet PHY Status LEDs
Direction Indicator DUP TX RX
Link Rate Mbps
100 1000 P1
VCC2V5
FPGA INIT and DONE LEDs
FPGAINITB
FPGADONE
16. User I/O
User LEDs User Pushbutton Switches User DIP Switch User SIP Header
User LEDs
User SMA GPIO
Figure 1-16 User Pushbutton Switch Typical
User Pushbutton Switches
Table 1-24 Pushbutton Switch Connections
Switch Pin
Figure 1-17 User DIP Switch S2 Table 1-25 User DIP Switch Connections
User DIP Switch
DIP Switch Pin
Schematic Net Name
Figure 1-18 User SIP Header J55
User SIP Header
Table 1-26 User SIP Header Connections
Schematic Net Name
Figure 1-19 User SMA GPIO
User SMA GPIO
Table 1-27 User SMA Connections
GPIO SMA Pin
Power On/Off Slide Switch SW2
17. Switches
Power On/Off Slide Switch SW2 FPGAPROGB Pushbutton SW3 Active-Low
SYSACERESETB Pushbutton SW9 Active-Low
Figure 1-22 System ACE CF RESETB Pushbutton SW9
SYSACERESETB Pushbutton SW9 Active-Low
FPGAPROGB Pushbutton SW3 Active-Low
Figure 1-21 FPGA PROGB Pushbutton SW3
Figure 1-23 System ACE CF CompactFlash Image Select DIP Switch S1
System ACE CF CompactFlash Image Select DIP Switch S1 Active-High
SDMX-4-X
Chapter 1 SP605 Evaluation Board
Figure 1-24 FPGA Mode DIP Switch SW1
Mode DIP Switch SW1 Active-High
R9 SDMX-2-X
References
Chapter 1 SP605 Evaluation Board
18. VITA 57.1 FMC LPC Connector
J63 FMC
Table 1-28 VITA 57.1 FMC LPC Connections
LPC Pin
Appendix B, “VITA 57.1 FMC LPC Connector Pinout.”
AC Adapter and 12V Input Power Jack/Switch
Power Management
Table 1-28 VITA 57.1 FMC LPC Connections Cont’d
Schematic Net Name
Power Management
Onboard Power Regulation
Power Supply
Figure 1-25 Onboard Power Regulators
Power Rail Net
Table 1-29 Onboard Power System Devices
Device Type
Reference
Configuration Options
Configuration Options
“5. System ACE CF and CompactFlash Connector,” page
Table 1-30 SP605 FPGA Configuration Modes
SP605 Hardware User Guide
Chapter 1 SP605 Evaluation Board
UG526 v1.1.1 February 1
Table A-1 Default Switch Settings
Default Jumper and Switch Settings
Default
Appendix A
Table A-2 Default Jumper Settings
Appendix A Default Jumper and Switch Settings
CF Error LED
Jumper
Figure B-1 FMC LPC Connector Pinout
VITA 57.1 FMC LPC Connector Pinout
Appendix B
UG526 v1.1.1 February 1
SP605 Hardware User Guide
Appendix B VITA 57.1 FMC LPC Connector Pinout
UG526 v1.1.1 February 1
Appendix C
SP605 Master UCF
UG526 v1.1.1 February 1
SP605 Hardware User Guide
Appendix C SP605 Master UCF
UG526 v1.1.1 February 1
LOC = AA20
UG526 v1.1.1 February 1
Appendix C SP605 Master UCF
3. Series resistors are included
SP605 Hardware User Guide
Appendix C SP605 Master UCF
UG526 v1.1.1 February 1
Appendix D
References