Xilinx SP605 USB-to-UART Bridge, 16 USB Type B Pin Assignments and Signal Definitions, References

Models: SP605

1 67
Download 67 pages 13.67 Kb
Page 33
Image 33
12. USB-to-UART Bridge

Detailed Description

12. USB-to-UART Bridge

The SP605 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U4) which allows connection to a host computer with a USB cable. The USB cable is supplied in this evaluation kit (Type A end to host computer, Type Mini-B end to SP605 connector J23). Table 1-16details the SP605 J23 pinout.

Xilinx UART IP is expected to be implemented in the FPGA fabric (for instance, Xilinx XPS UART Lite). The FPGA supports the USB-to-UART bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS).

Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers which permit the CP2103GM USB-to-UART bridge to appear as a COM port to host computer communications application software (for example, HyperTerm or TeraTerm). The VCP device driver must be installed on the host PC prior to establishing communications with the SP605. Refer to the evaluation kit Getting Started Guide for driver installation instructions.

Table 1-16:USB Type B Pin Assignments and Signal Definitions

USB Connector

Signal Name

 

Description

 

Pin

 

 

 

 

 

 

 

 

 

 

 

1

VBUS

+5V from host system (not used)

 

 

 

 

 

 

2

USB_DATA_N

Bidirectional differential serial data (N-side)

 

 

 

 

 

3

USB_DATA_P

Bidirectional differential serial data (P-side)

 

 

 

 

 

4

GROUND

Signal ground

 

 

 

 

 

 

 

Table 1-17:USB-to-UART Connections

 

 

 

 

 

 

 

U1 FPGA Pin

UART Function

Schematic Net

U30 CP2103GM

UART Function

in FPGA

Name

Pin

in CP2103GM

 

 

 

 

 

 

F18

RTS, output

USB_1_CTS

22

CTS, input

 

 

 

 

 

F19

CTS, input

USB_1_RTS

23

RTS, output

 

 

 

 

 

B21

TX, data out

USB_1_RX

24

RXD, data in

 

 

 

 

 

H17

RX, data in

USB_1_TX

25

TXD, data out

 

 

 

 

 

Notes:

1.The schematic net names correspond with the CP2103GM pin names and functions, and the UART IP in the FPGA must be connected accordingly.

References

Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers.

In addition, see some of the Xilinx UART IP specifications at:

http://www.xilinx.com/support/documentation/ip_documentation/xps_uartlite.pdf

http://www.xilinx.com/support/documentation/ip_documentation/xps_uart16550.pdf

SP605 Hardware User Guide

www.xilinx.com

33

UG526 (v1.1.1) February 1, 2010

Page 33
Image 33
Xilinx SP605 manual USB-to-UART Bridge, 16 USB Type B Pin Assignments and Signal Definitions, USB Connector, Description