Table A-1Default Switch Settings | Xilinx SP605 specification

Appendix A

Default Jumper and Switch Settings

Table A-1shows the default switch settings and Table A-2, page 58 shows the default jumper settings for the SP605.

Table A-1:Default Switch Settings

REFDES			Function/Type	Default

SW2		Board power slide-switch		off

	FPGA mode 2-pole DIP switch, Slave SelectMAP
	default selects System ACE CF configuration
SW1
SW1	2		M1 = 1	on
	2		M1 = 1	on

	1		M0 = 0	off

	System ACE CF configuration and image select
		4-pole DIP switch

	4		SysAce Mode = 1	on
S1
S1	3		SysAce CFGAddr2 = 0	off
	3		SysAce CFGAddr2 = 0	off

	2		SysAce CFGAddr1 = 0	off

	1		SysAce CFGAddr0 = 0	off

		User GPIO 4-pole DIP switch

	4			off
S2
S2	3			off

	2			off

	1			off

SP605 Hardware User Guide

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UG526 (v1.1.1) February 1, 2010

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Xilinx SP605 manual Table A-1Default Switch Settings, Function/Type Default

Contents

UG526 v1.1.1 February 1, 2010 optional SP605 Hardware User Guide Date Version Revision Revision History Table of Contents SP605 Hardware User Guide About This Guide Preface About This Guide Additional Support Resources Additional Information SP605 Evaluation Board SP605 Evaluation Board Features Overview Block Diagram Feature SP605 Features Detailed Description SP605 Features Cont’d Configuration SP605 Evaluation Board SP605 Features Cont’dSpartan-6 XC6SLX45T-3FGG484 Fpga Voltage Rails MB DDR3 Component MemoryDetailed Description 2I/O Voltage Rail of Fpga Banks 5DDR3 Component Memory Connections Schematic Net Name Memory U42 Pin Pin Number Pin Name U1 Fpga 3J17 SPI Flash Programming Header SPI x4 Flash Detailed Description 6SPI x4 Memory Connections Schematic Net Name Pin Number Pin Name Linear BPI Flash FLASHA16 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector U17 XCCACETQ144I 8System ACE CF Connections U1 Fpga Pin Schematic Net Name1 USB Jtag Oscillator Differential Clock Generation 8SP605 X2 Oscillator Socket Pin 1 Location Identifiers Oscillator Socket Single-Ended, 2.5V or Multi-Gigabit Transceivers GTP MGTs SMA Connectors Differential MGT Refclk Smarefclkn 11PCIe Edge Connector Connections U1 Fpga Pin P4 PCIe Edge ConnectorPCI Express Endpoint Connectivity References Sfpclkqop SFP Module Connector 11 /100/1000 Tri-Speed Ethernet PHY 14PHY Configuration PinsBit2 Bit1 Bit0 15Ethernet PHY Connections U1 Fpga Pin PHYRXD7 17 USB-to-UART Connections USB-to-UART Bridge DVI Codec 11IIC Bus Topology IIC Bus Iicsclsfp Kb NV Memory Iicsdamain SDA Status LEDs Signal Name Color Label Description 13Ethernet PHY Status LEDs Ethernet PHY Status LEDs 22 Fpga Init and Done LED Connections Fpga Init and Done LEDs User LEDs User I/O23User LED Connections U1 Fpga Pin Controlled LED SW6 User Pushbutton Switches User DIP Switch U1 Fpga Pin User SIP Header Usersmagpion Usersmagpiop User SMA Gpio Power On/Off Slide Switch SW2 Switches Fpgaprogb Pushbutton SW3 Active-Low Sysaceresetb Pushbutton SW9 Active-Low 23System ACE CF CompactFlash Image Select DIP Switch S1 24FPGA Mode DIP Switch SW1 Mode DIP Switch SW1 Active-High Vita 57.1 FMC LPC Connector LPC Pin 28VITA 57.1 FMC LPC Connections AC Adapter and 12V Input Power Jack/Switch Power Management Power Management Onboard Power Regulation UCD9240PFC Configuration Options 30SP605 Fpga Configuration Modes M10 Bus WidthConfiguration Solution User Guide Section SP605 Evaluation Board Function/Type Default Table A-1Default Switch Settings FMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF NET Fmcpwrgoodflashrstb Appendix C SP605 Master UCF NET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References