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Xilinx SP605 Default Jumper and Switch Settings, Appendix A, Table A-1 Default Switch Settings

Models: SP605

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Appendix A

Default Jumper and Switch Settings

Table A-1shows the default switch settings and Table A-2, page 58 shows the default jumper settings for the SP605.

Table A-1:Default Switch Settings

REFDES			Function/Type	Default

SW2		Board power slide-switch		off

	FPGA mode 2-pole DIP switch, Slave SelectMAP
	default selects System ACE CF configuration
SW1
SW1	2		M1 = 1	on
	2		M1 = 1	on

	1		M0 = 0	off

	System ACE CF configuration and image select
		4-pole DIP switch

	4		SysAce Mode = 1	on
S1
S1	3		SysAce CFGAddr2 = 0	off
	3		SysAce CFGAddr2 = 0	off

	2		SysAce CFGAddr1 = 0	off

	1		SysAce CFGAddr0 = 0	off

		User GPIO 4-pole DIP switch

	4			off
S2
S2	3			off

	2			off

	1			off

SP605 Hardware User Guide

www.xilinx.com

UG526 (v1.1.1) February 1, 2010

Page 57

Image 57

Xilinx SP605 Default Jumper and Switch Settings, Appendix A, Table A-1 Default Switch Settings, Refdes, Function/Type

Contents

UG526 v1.1.1 February 1, 2010 optional SP605 Hardware User GuideGuide Subtitle optional Revision History Updated Figure 1-17 and FigureDate VersionTable of Contents Preface About This GuideChapter 1 SP605 Evaluation Board Appendix B VITA 57.1 FMC LPC Connector Pinout Appendix A Default Jumper and Switch SettingsAppendix C SP605 Master UCF Appendix D References Mode DIP Switch SW1 Active-High 18. VITA 57.1 FMC LPC ConnectorAppendix A, “Default Jumper and Switch Settings.” Guide ContentsAppendix B, “VITA 57.1 FMC LPC Connector Pinout.” About This GuidePreface About This Guide Additional Support ResourcesChapter SP605 Evaluation BoardOverview Additional Information5. System ACE CF and CompactFlash Connector 6. USB JTAG Features10. SFP Module Connector 11. 10/100/1000 Tri-Speed Ethernet PHY Chapter 1 SP605 Evaluation Board17. Switches Block Diagram18. VITA 57.1 FMC LPC Connector Configuration Options 4. Linear BPI Flash 5. System ACE CF and CompactFlash ConnectorFeature SP605 FeaturesRelated Xilinx Documents Detailed DescriptionDetailed Description SP605 Features Cont’dFeature Linear BPI Flash1. Spartan-6 XC6SLX45T-3FGG484 FPGA ConfigurationReferences SP605 Features Cont’d2. 128 MB DDR3 Component Memory Signal NameI/O Voltage Rails Table 1-2 I/O Voltage Rail of FPGA BanksTable 1-4 FPGA On-Chip OCT Termination External Resistor Requirements Schematic Net NameU1 FPGA Pin FPGA Pin NumberReferences DDR3 Component Memory Connections Cont’dDetailed Description Memory U42Silkscreen 3. SPI x4 FlashFigure 1-3 J17 SPI Flash Programming Header Figure 1-4 SPI Flash Interface TopologySPI MEM U32 Detailed Description Table 1-6 SPI x4 Memory ConnectionsSPI HDR J17 Schematic Net NameFigure 1-5 Linear BPI Flash Interface 4. Linear BPI FlashTable 1-7 Linear Flash Connections U25 BPI FLASHSchematic Net Name Detailed Description Table 1-7 Linear Flash Connections Cont’dU1 FPGA Pin U25 BPI FLASHFPGA Design Considerations for the Configuration Flash 5. System ACE CF and CompactFlash ConnectorReferences Chapter 1 SP605 Evaluation BoardTable 1-8 System ACE CF Connections Schematic Net Name1U17 XCCACETQ144I Detailed Description6. USB JTAG Figure 1-6 JTAG Chain DiagramTable 1-8 System ACE CF Connections Cont’d Schematic Net NameOscillator Differential 7. Clock GenerationFigure 1-7 VITA 57.1 FMC LPC J2 JTAG Bypass Jumper J19 ReferencesFigure 1-8 SP605 X2 Oscillator Socket Pin 1 Location Identifiers Oscillator Socket Single-Ended, 2.5V orFigure 1-9 SP605 X2 Oscillator Pin 1 Location Identifiers Silkscreened outline has beveled corner Socket has notch in crossbar8. Multi-Gigabit Transceivers GTP MGTs SMA Connectors DifferentialTable 1-9 SP605 Clock Source Connections SourceSMA MGT Connectors Figure 1-10 GTP SMA ClockMGT REFCLK Chapter 1 SP605 Evaluation BoardSMA Pin Detailed Description Table 1-10 GTP SMA Clock ConnectionsSchematic Net Name U1 FPGA PinP4 PCIe Edge Connector Table 1-11 PCIe Edge Connector Connections9. PCI Express Endpoint Connectivity Chapter 1 SP605 Evaluation BoardReferences Detailed DescriptionProduct information SFP Control/Status Signal 10. SFP Module ConnectorP2 SFP Module Connector Table 1-12 SFP Module Control and Status11. 10/100/1000 Tri-Speed Ethernet PHY Table 1-14 PHY Configuration PinsBit2 Bit1References Table 1-15 Ethernet PHY Connections Cont’dChapter 1 SP605 Evaluation Board U1 FPGA PinUSB Connector Table 1-16 USB Type B Pin Assignments and Signal Definitions12. USB-to-UART Bridge Description13. DVI CODEC Schematic NetTable 1-18 DVI Controller Connections U31 Chrontel CH7301C14. IIC Bus Figure 1-11 IIC Bus TopologyDetailed Description External Access Schematic8-Kb NV Memory Table 1-19 IIC Bus ConnectionsDetailed Description Table 1-20 IIC Memory Connections Schematic NetnameIIC Memory U4 ReferencesTable 1-21 Status LEDs 15. Status LEDsColor LabelEthernet PHY Status LEDs Direction Indicator DUP TX RXLink Rate Mbps 100 1000 P1VCC2V5 FPGA INIT and DONE LEDsFPGAINITB FPGADONE16. User I/O User LEDs User Pushbutton Switches User DIP Switch User SIP HeaderUser LEDs User SMA GPIOFigure 1-16 User Pushbutton Switch Typical User Pushbutton SwitchesTable 1-24 Pushbutton Switch Connections Switch PinFigure 1-17 User DIP Switch S2 Table 1-25 User DIP Switch Connections User DIP SwitchDIP Switch Pin Schematic Net NameFigure 1-18 User SIP Header J55 User SIP HeaderTable 1-26 User SIP Header Connections Schematic Net NameFigure 1-19 User SMA GPIO User SMA GPIOTable 1-27 User SMA Connections GPIO SMA PinPower On/Off Slide Switch SW2 17. SwitchesPower On/Off Slide Switch SW2 FPGAPROGB Pushbutton SW3 Active-Low SYSACERESETB Pushbutton SW9 Active-LowFigure 1-22 System ACE CF RESETB Pushbutton SW9 SYSACERESETB Pushbutton SW9 Active-LowFPGAPROGB Pushbutton SW3 Active-Low Figure 1-21 FPGA PROGB Pushbutton SW3Figure 1-23 System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1 Active-HighSDMX-4-X Chapter 1 SP605 Evaluation BoardFigure 1-24 FPGA Mode DIP Switch SW1 Mode DIP Switch SW1 Active-HighR9 SDMX-2-X ReferencesChapter 1 SP605 Evaluation Board 18. VITA 57.1 FMC LPC ConnectorJ63 FMC Table 1-28 VITA 57.1 FMC LPC ConnectionsLPC Pin Appendix B, “VITA 57.1 FMC LPC Connector Pinout.”AC Adapter and 12V Input Power Jack/Switch Power ManagementTable 1-28 VITA 57.1 FMC LPC Connections Cont’d Schematic Net NamePower Management Onboard Power RegulationPower Supply Figure 1-25 Onboard Power RegulatorsPower Rail Net Table 1-29 Onboard Power System DevicesDevice Type ReferenceConfiguration Options Configuration Options“5. System ACE CF and CompactFlash Connector,” page Table 1-30 SP605 FPGA Configuration ModesChapter 1 SP605 Evaluation Board SP605 Hardware User GuideUG526 v1.1.1 February 1 Table A-1 Default Switch Settings Default Jumper and Switch SettingsDefault Appendix ATable A-2 Default Jumper Settings Appendix A Default Jumper and Switch SettingsCF Error LED JumperFigure B-1 FMC LPC Connector Pinout VITA 57.1 FMC LPC Connector PinoutAppendix B UG526 v1.1.1 February 1Appendix B VITA 57.1 FMC LPC Connector Pinout SP605 Hardware User GuideUG526 v1.1.1 February 1 SP605 Master UCF Appendix CUG526 v1.1.1 February 1 Appendix C SP605 Master UCF SP605 Hardware User GuideUG526 v1.1.1 February 1 LOC = AA20 UG526 v1.1.1 February 1Appendix C SP605 Master UCF 3. Series resistors are included Appendix C SP605 Master UCF SP605 Hardware User GuideUG526 v1.1.1 February 1 Appendix D References

Appendix A

Default Jumper and Switch Settings

Table A-1:Default Switch Settings

REFDES

Function/Type

Default