Fpgaprogb Pushbutton SW3 Active-Low | Xilinx SP605 specification

Detailed Description

FPGA_PROG_B Pushbutton SW3 (Active-Low)

The SW3 switch (Figure 1-21) grounds the FPGA PROG_B pin when pressed. This action clears the FPGA. See the Spartan-6 FPGA data sheet for more information on clearing the contents of the FPGA.

VCC2V5

1 R17

4.7K

5%

2 1/16W

	Pushbutton
FPGA_PROG_B	1		P1	P4	4
	2		P2	P3	3
			P2	P3
		SW3

UG526_21 _092409

Figure 1-21:FPGA PROG_B Pushbutton SW3

SYSACE_RESET_B Pushbutton SW9 (Active-Low)

When the System ACE CF configuration mode pin is high (enabled by closing DIP switch S1 switch 4), the System ACE CF controller configures the FPGA from the CompactFlash card when a card is inserted or the SYSACE RESET button is pressed. See “5. System ACE CF and CompactFlash Connector,” page 20 for more details.

	Silkscreen:
SYSACE_RESET_B 20		"SYSACE RESET"
SYSACE_RESET_B 20
	Pushbutton
1		P1	P4	4
	2	P2	P3	3
		P2	P3
		SW9

UG526_22 _092409

Figure 1-22:System ACE CF RESET_B Pushbutton SW9

SP605 Hardware User Guide

www.xilinx.com

47

UG526 (v1.1.1) February 1, 2010

Image 47

Xilinx SP605 manual Fpgaprogb Pushbutton SW3 Active-Low, Sysaceresetb Pushbutton SW9 Active-Low

Contents

UG526 v1.1.1 February 1, 2010 optional SP605 Hardware User Guide Date Version Revision Revision History Table of Contents SP605 Hardware User Guide About This Guide Preface About This Guide Additional Support Resources Additional Information SP605 Evaluation Board SP605 Evaluation Board Features Overview Block Diagram Feature SP605 Features Detailed Description SP605 Features Cont’d Spartan-6 XC6SLX45T-3FGG484 Fpga ConfigurationSP605 Evaluation Board SP605 Features Cont’d 2I/O Voltage Rail of Fpga Banks MB DDR3 Component MemoryVoltage Rails Detailed Description 5DDR3 Component Memory Connections Schematic Net Name Memory U42 Pin Pin Number Pin Name U1 Fpga 3J17 SPI Flash Programming Header SPI x4 Flash Detailed Description 6SPI x4 Memory Connections Schematic Net Name Pin Number Pin Name Linear BPI Flash FLASHA16 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector U17 XCCACETQ144I 8System ACE CF Connections U1 Fpga Pin Schematic Net Name1 USB Jtag Oscillator Differential Clock Generation 8SP605 X2 Oscillator Socket Pin 1 Location Identifiers Oscillator Socket Single-Ended, 2.5V or Multi-Gigabit Transceivers GTP MGTs SMA Connectors Differential MGT Refclk Smarefclkn PCI Express Endpoint Connectivity 11PCIe Edge Connector Connections U1 Fpga PinP4 PCIe Edge Connector References Sfpclkqop SFP Module Connector 15Ethernet PHY Connections U1 Fpga Pin 14PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0 PHYRXD7 17 USB-to-UART Connections USB-to-UART Bridge DVI Codec 11IIC Bus Topology IIC Bus Iicsclsfp Kb NV Memory Iicsdamain SDA Status LEDs Signal Name Color Label Description 13Ethernet PHY Status LEDs Ethernet PHY Status LEDs 22 Fpga Init and Done LED Connections Fpga Init and Done LEDs Controlled LED User I/OUser LEDs 23User LED Connections U1 Fpga Pin SW6 User Pushbutton Switches User DIP Switch U1 Fpga Pin User SIP Header Usersmagpion Usersmagpiop User SMA Gpio Power On/Off Slide Switch SW2 Switches Fpgaprogb Pushbutton SW3 Active-Low Sysaceresetb Pushbutton SW9 Active-Low 23System ACE CF CompactFlash Image Select DIP Switch S1 24FPGA Mode DIP Switch SW1 Mode DIP Switch SW1 Active-High Vita 57.1 FMC LPC Connector LPC Pin 28VITA 57.1 FMC LPC Connections AC Adapter and 12V Input Power Jack/Switch Power Management Power Management Onboard Power Regulation UCD9240PFC Configuration Solution User Guide Section Configuration Options30SP605 Fpga Configuration Modes M10 Bus Width SP605 Evaluation Board Function/Type Default Table A-1Default Switch Settings FMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF NET Fmcpwrgoodflashrstb Appendix C SP605 Master UCF NET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References