FLASHA16 | Xilinx SP605 guide

Detailed Description

Table 1-7:Linear Flash Connections (Cont’d)

	U1 FPGA Pin	Schematic Net Name	U25 BPI FLASH

			Pin Number	Pin Name
			Pin Number	Pin Name

	E22	FLASH_A16	55	A17

	E20	FLASH_A17	18	A18

	F22	FLASH_A18	17	A19

	F21	FLASH_A19	16	A20

	H19	FLASH_A20	11	A21

	H18	FLASH_A21	10	A22

	F20	FLASH_A22	9	A23

	G19	FLASH_A23	26	A24


	AA20	FPGA_D0_DIN_MISO_MISO1	34	DQ0

	R13	FPGA_D1_MISO2	36	DQ1

	T14	FPGA_D2_MISO3	39	DQ2

	AA6	FLASH_D3	41	DQ3

	AB6	FLASH_D4	47	DQ4

	Y5	FLASH_D5	49	DQ5

	AB5	FLASH_D6	51	DQ6

	W9	FLASH_D7	53	DQ7

	T7	FLASH_D8	35	DQ8

	U6	FLASH_D9	37	DQ9

	AB19	FLASH_D10	40	DQ10

	AA18	FLASH_D11	42	DQ11

	AB18	FLASH_D12	48	DQ12

	Y13	FLASH_D13	50	DQ13

	AA12	FLASH_D14	52	DQ14

	AB12	FLASH_D15	54	DQ15


	V13	FMC_PWR_GOOD_FLASH_RST_B	44	RST_B

	R20	FLASH_WE_B	14	WE_B

	P22	FLASH_OE_B	32	OE_B

	P21	FLASH_CE_B	30	CE_B

	T19	FLASH_ADV_B	46	ADV_B

	T18	FLASH_WAIT	56	WAIT

SP605 Hardware User Guide

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UG526 (v1.1.1) February 1, 2010

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Xilinx SP605 manual FLASHA16

Contents

UG526 v1.1.1 February 1, 2010 optional SP605 Hardware User Guide Date Version Revision Revision History Table of Contents SP605 Hardware User Guide About This Guide Preface About This Guide Additional Support Resources Additional Information SP605 Evaluation Board SP605 Evaluation Board Features Overview Block Diagram Feature SP605 Features Detailed Description SP605 Features Cont’d SP605 Evaluation Board SP605 Features Cont’d ConfigurationSpartan-6 XC6SLX45T-3FGG484 Fpga 2I/O Voltage Rail of Fpga Banks MB DDR3 Component MemoryVoltage Rails Detailed Description 5DDR3 Component Memory Connections Schematic Net Name Memory U42 Pin Pin Number Pin Name U1 Fpga 3J17 SPI Flash Programming Header SPI x4 Flash Detailed Description 6SPI x4 Memory Connections Schematic Net Name Pin Number Pin Name Linear BPI Flash FLASHA16 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector U17 XCCACETQ144I 8System ACE CF Connections U1 Fpga Pin Schematic Net Name1 USB Jtag Oscillator Differential Clock Generation 8SP605 X2 Oscillator Socket Pin 1 Location Identifiers Oscillator Socket Single-Ended, 2.5V or Multi-Gigabit Transceivers GTP MGTs SMA Connectors Differential MGT Refclk Smarefclkn P4 PCIe Edge Connector 11PCIe Edge Connector Connections U1 Fpga PinPCI Express Endpoint Connectivity References Sfpclkqop SFP Module Connector 15Ethernet PHY Connections U1 Fpga Pin 14PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0 PHYRXD7 17 USB-to-UART Connections USB-to-UART Bridge DVI Codec 11IIC Bus Topology IIC Bus Iicsclsfp Kb NV Memory Iicsdamain SDA Status LEDs Signal Name Color Label Description 13Ethernet PHY Status LEDs Ethernet PHY Status LEDs 22 Fpga Init and Done LED Connections Fpga Init and Done LEDs Controlled LED User I/OUser LEDs 23User LED Connections U1 Fpga Pin SW6 User Pushbutton Switches User DIP Switch U1 Fpga Pin User SIP Header Usersmagpion Usersmagpiop User SMA Gpio Power On/Off Slide Switch SW2 Switches Fpgaprogb Pushbutton SW3 Active-Low Sysaceresetb Pushbutton SW9 Active-Low 23System ACE CF CompactFlash Image Select DIP Switch S1 24FPGA Mode DIP Switch SW1 Mode DIP Switch SW1 Active-High Vita 57.1 FMC LPC Connector LPC Pin 28VITA 57.1 FMC LPC Connections AC Adapter and 12V Input Power Jack/Switch Power Management Power Management Onboard Power Regulation UCD9240PFC 30SP605 Fpga Configuration Modes M10 Bus Width Configuration OptionsConfiguration Solution User Guide Section SP605 Evaluation Board Function/Type Default Table A-1Default Switch Settings FMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF NET Fmcpwrgoodflashrstb Appendix C SP605 Master UCF NET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References