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Xilinx 18 User SIP Header J55, 26 User SIP Header Connections, SP605 Evaluation Board

Models: SP605

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User SIP Header

Chapter 1: SP605 Evaluation Board

User SIP Header

The SP605 includes a 6-pin single-inline (SIP) male pin header (J55) for FPGA GPIO access. Four pins of J55 are wired to the FPGA through 200 ohm series resistors and a level shifter, and the remaining two J55 pins are wired to 3.3V and GND. The J55 header is described in Figure 1-18and Table 1-26.

Note: This header is not installed on the SP605 as built.

VCC1V5_FPGAVCC3V3

U52

U1 FPGA Pin

2

VCCA

G7

GPIO_HEADER_0_LS

1

A1

GPIO_HEADER_1_LS

3

H6

A2

GPIO_HEADER_2_LS

4

D1

A3

R7

GPIO_HEADER_3_LS

5

A4

NC

6

A5

NC

7

A6

NC

8

A7

NC

9

A8

10

OE

TXB0108

C385

X5R

1

VCCB 1920

B1

B2 18

B3 17

B4 16

B5 15

B6 14

B7 13

B8 12

GND 11

10V	0.1UF

2

GPIO_HEADER_0 GPIO_HEADER_1 GPIO_HEADER_2 GPIO_HEADER_3

NC

NC

NC

NC

1C384

X5R

210V

0.1UF

	GPIO_HEADER_0	R280	200	5%	1/16W	R281		1/16W
		1			2		200 5%
	GPIO_HEADER_1
		R282	200	5%	1/16W	1		2
	GPIO_HEADER_2
		1			2	R283	200 5%	1/16W
	GPIO_HEADER_3
						1		2

HDR_1x6

J55

1

2

3

4

5

6

DNP

VCC3V3

UG526_18 _092409

Figure 1-18:User SIP Header J55

Table 1-26:User SIP Header Connections

U1 FPGA Pin	Schematic Net Name	GPIO Header Pin

G7	GPIO_HEADER_0	J55.1

H6	GPIO_HEADER_1	J55.2

D1	GPIO_HEADER_2	J55.3

R7	GPIO_HEADER_3	J55.4

–	GND	J55.5

–	VCC3V3	J55.6

Notes:

1.Each GPIO_HEADER_n signal is sourced from the FPGA as <netname>_LS to a level shifter, then to the J55 header.

2.Each GPIO_HEADER_n net has a 200 ohm series resistor between the level shifter and its respective header pin.

44	www.xilinx.com	SP605 Hardware User Guide
		UG526 (v1.1.1) February 1, 2010

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Xilinx manual 18 User SIP Header J55, 26 User SIP Header Connections, SP605 Evaluation Board, U1 FPGA Pin

Contents

Guide Subtitle optional UG526 v1.1.1 February 1, 2010 optionalSP605 Hardware User Guide Updated Figure 1-17 and Figure Revision HistoryDate VersionChapter 1 SP605 Evaluation Board Table of ContentsPreface About This Guide Appendix A Default Jumper and Switch Settings Appendix B VITA 57.1 FMC LPC Connector PinoutAppendix C SP605 Master UCF Appendix D References Mode DIP Switch SW1 Active-High 18. VITA 57.1 FMC LPC ConnectorGuide Contents Appendix A, “Default Jumper and Switch Settings.”Appendix B, “VITA 57.1 FMC LPC Connector Pinout.” About This GuideAdditional Support Resources Preface About This GuideSP605 Evaluation Board ChapterOverview Additional InformationFeatures 5. System ACE CF and CompactFlash Connector 6. USB JTAG10. SFP Module Connector 11. 10/100/1000 Tri-Speed Ethernet PHY Chapter 1 SP605 Evaluation BoardBlock Diagram 17. Switches18. VITA 57.1 FMC LPC Connector Configuration Options 4. Linear BPI Flash 5. System ACE CF and CompactFlash ConnectorSP605 Features FeatureRelated Xilinx Documents Detailed DescriptionSP605 Features Cont’d Detailed DescriptionFeature Linear BPI FlashConfiguration 1. Spartan-6 XC6SLX45T-3FGG484 FPGAReferences SP605 Features Cont’dSignal Name 2. 128 MB DDR3 Component MemoryI/O Voltage Rails Table 1-2 I/O Voltage Rail of FPGA BanksSchematic Net Name Table 1-4 FPGA On-Chip OCT Termination External Resistor RequirementsU1 FPGA Pin FPGA Pin NumberDDR3 Component Memory Connections Cont’d ReferencesDetailed Description Memory U423. SPI x4 Flash SilkscreenFigure 1-3 J17 SPI Flash Programming Header Figure 1-4 SPI Flash Interface TopologyDetailed Description Table 1-6 SPI x4 Memory Connections SPI MEM U32SPI HDR J17 Schematic Net Name4. Linear BPI Flash Figure 1-5 Linear BPI Flash InterfaceTable 1-7 Linear Flash Connections U25 BPI FLASHDetailed Description Table 1-7 Linear Flash Connections Cont’d Schematic Net NameU1 FPGA Pin U25 BPI FLASH5. System ACE CF and CompactFlash Connector FPGA Design Considerations for the Configuration FlashReferences Chapter 1 SP605 Evaluation BoardSchematic Net Name1 Table 1-8 System ACE CF ConnectionsU17 XCCACETQ144I Detailed DescriptionFigure 1-6 JTAG Chain Diagram 6. USB JTAGTable 1-8 System ACE CF Connections Cont’d Schematic Net Name7. Clock Generation Oscillator DifferentialFigure 1-7 VITA 57.1 FMC LPC J2 JTAG Bypass Jumper J19 ReferencesOscillator Socket Single-Ended, 2.5V or Figure 1-8 SP605 X2 Oscillator Socket Pin 1 Location IdentifiersFigure 1-9 SP605 X2 Oscillator Pin 1 Location Identifiers Silkscreened outline has beveled corner Socket has notch in crossbarSMA Connectors Differential 8. Multi-Gigabit Transceivers GTP MGTsTable 1-9 SP605 Clock Source Connections SourceFigure 1-10 GTP SMA Clock SMA MGT ConnectorsMGT REFCLK Chapter 1 SP605 Evaluation BoardDetailed Description Table 1-10 GTP SMA Clock Connections SMA PinSchematic Net Name U1 FPGA PinTable 1-11 PCIe Edge Connector Connections P4 PCIe Edge Connector9. PCI Express Endpoint Connectivity Chapter 1 SP605 Evaluation BoardProduct information ReferencesDetailed Description 10. SFP Module Connector SFP Control/Status SignalP2 SFP Module Connector Table 1-12 SFP Module Control and StatusTable 1-14 PHY Configuration Pins 11. 10/100/1000 Tri-Speed Ethernet PHYBit2 Bit1Table 1-15 Ethernet PHY Connections Cont’d ReferencesChapter 1 SP605 Evaluation Board U1 FPGA PinTable 1-16 USB Type B Pin Assignments and Signal Definitions USB Connector12. USB-to-UART Bridge DescriptionSchematic Net 13. DVI CODECTable 1-18 DVI Controller Connections U31 Chrontel CH7301CDetailed Description 14. IIC BusFigure 1-11 IIC Bus Topology Schematic External Access8-Kb NV Memory Table 1-19 IIC Bus ConnectionsSchematic Netname Detailed Description Table 1-20 IIC Memory ConnectionsIIC Memory U4 References15. Status LEDs Table 1-21 Status LEDsColor LabelDirection Indicator DUP TX RX Ethernet PHY Status LEDsLink Rate Mbps 100 1000 P1FPGA INIT and DONE LEDs VCC2V5FPGAINITB FPGADONEUser LEDs User Pushbutton Switches User DIP Switch User SIP Header 16. User I/OUser LEDs User SMA GPIOUser Pushbutton Switches Figure 1-16 User Pushbutton Switch TypicalTable 1-24 Pushbutton Switch Connections Switch PinUser DIP Switch Figure 1-17 User DIP Switch S2 Table 1-25 User DIP Switch ConnectionsDIP Switch Pin Schematic Net NameUser SIP Header Figure 1-18 User SIP Header J55Table 1-26 User SIP Header Connections Schematic Net NameUser SMA GPIO Figure 1-19 User SMA GPIOTable 1-27 User SMA Connections GPIO SMA Pin17. Switches Power On/Off Slide Switch SW2Power On/Off Slide Switch SW2 FPGAPROGB Pushbutton SW3 Active-Low SYSACERESETB Pushbutton SW9 Active-LowSYSACERESETB Pushbutton SW9 Active-Low Figure 1-22 System ACE CF RESETB Pushbutton SW9FPGAPROGB Pushbutton SW3 Active-Low Figure 1-21 FPGA PROGB Pushbutton SW3System ACE CF CompactFlash Image Select DIP Switch S1 Active-High Figure 1-23 System ACE CF CompactFlash Image Select DIP Switch S1SDMX-4-X Chapter 1 SP605 Evaluation BoardMode DIP Switch SW1 Active-High Figure 1-24 FPGA Mode DIP Switch SW1R9 SDMX-2-X References18. VITA 57.1 FMC LPC Connector Chapter 1 SP605 Evaluation BoardTable 1-28 VITA 57.1 FMC LPC Connections J63 FMCLPC Pin Appendix B, “VITA 57.1 FMC LPC Connector Pinout.”Power Management AC Adapter and 12V Input Power Jack/SwitchTable 1-28 VITA 57.1 FMC LPC Connections Cont’d Schematic Net NameOnboard Power Regulation Power ManagementPower Supply Figure 1-25 Onboard Power RegulatorsTable 1-29 Onboard Power System Devices Power Rail NetDevice Type ReferenceConfiguration Options Configuration Options“5. System ACE CF and CompactFlash Connector,” page Table 1-30 SP605 FPGA Configuration ModesUG526 v1.1.1 February 1 Chapter 1 SP605 Evaluation BoardSP605 Hardware User Guide Default Jumper and Switch Settings Table A-1 Default Switch SettingsDefault Appendix AAppendix A Default Jumper and Switch Settings Table A-2 Default Jumper SettingsCF Error LED JumperVITA 57.1 FMC LPC Connector Pinout Figure B-1 FMC LPC Connector PinoutAppendix B UG526 v1.1.1 February 1UG526 v1.1.1 February 1 Appendix B VITA 57.1 FMC LPC Connector PinoutSP605 Hardware User Guide UG526 v1.1.1 February 1 SP605 Master UCFAppendix C UG526 v1.1.1 February 1 Appendix C SP605 Master UCFSP605 Hardware User Guide UG526 v1.1.1 February 1 LOC = AA20Appendix C SP605 Master UCF 3. Series resistors are included UG526 v1.1.1 February 1 Appendix C SP605 Master UCFSP605 Hardware User Guide References Appendix D