FMC Jtag | Xilinx SP605 specs

Appendix A: Default Jumper and Switch Settings

Table A-2:Default Jumper Settings

	Jumper	Function	Default
	REFDES	Function	Default
	REFDES

	FMC JTAG
	Bypass

	J19	exclude FMC LPC connector J2	Jump 1-2

	SFP Module

	J22	SFP Full BW	Jump 1-2

	J44	SFP Enabled	Jump 1-2

	SPI Memory
	Select

	J46	SPI Select SPI X4 Memory U32	Jump 1-2

	System ACE
	CF Error LED

	J60	System ACE CF Error LED DS18 Enabled	Jump 1-2

58	www.xilinx.com	SP605 Hardware User Guide
		UG526 (v1.1.1) February 1, 2010

Image 58

Xilinx SP605 manual FMC Jtag

Contents

SP605 Hardware User Guide UG526 v1.1.1 February 1, 2010 optional Revision History Date Version Revision Table of Contents SP605 Hardware User Guide About This Guide Additional Support Resources Preface About This Guide SP605 Evaluation Board Additional Information Features SP605 Evaluation Board Block Diagram Overview SP605 Features Feature Detailed Description SP605 Features Cont’d SP605 Evaluation Board SP605 Features Cont’d ConfigurationSpartan-6 XC6SLX45T-3FGG484 Fpga Detailed Description MB DDR3 Component MemoryVoltage Rails 2I/O Voltage Rail of Fpga Banks Schematic Net Name Memory U42 Pin Pin Number Pin Name 5DDR3 Component Memory Connections U1 Fpga SPI x4 Flash 3J17 SPI Flash Programming Header Schematic Net Name Detailed Description 6SPI x4 Memory Connections Linear BPI Flash Pin Number Pin Name FLASHA16 System ACE CF and CompactFlash Connector Fpga Design Considerations for the Configuration Flash 8System ACE CF Connections U1 Fpga Pin Schematic Net Name1 U17 XCCACETQ144I USB Jtag Clock Generation Oscillator Differential Oscillator Socket Single-Ended, 2.5V or 8SP605 X2 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential Multi-Gigabit Transceivers GTP MGTs MGT Refclk Smarefclkn P4 PCIe Edge Connector 11PCIe Edge Connector Connections U1 Fpga PinPCI Express Endpoint Connectivity References SFP Module Connector Sfpclkqop Bit2 Bit1 Bit0 14PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY 15Ethernet PHY Connections U1 Fpga Pin PHYRXD7 USB-to-UART Bridge 17 USB-to-UART Connections DVI Codec IIC Bus 11IIC Bus Topology Kb NV Memory Iicsclsfp Iicsdamain SDA Signal Name Color Label Description Status LEDs Ethernet PHY Status LEDs 13Ethernet PHY Status LEDs Fpga Init and Done LEDs 22 Fpga Init and Done LED Connections 23User LED Connections U1 Fpga Pin User I/OUser LEDs Controlled LED User Pushbutton Switches SW6 User DIP Switch User SIP Header U1 Fpga Pin User SMA Gpio Usersmagpion Usersmagpiop Switches Power On/Off Slide Switch SW2 Sysaceresetb Pushbutton SW9 Active-Low Fpgaprogb Pushbutton SW3 Active-Low 23System ACE CF CompactFlash Image Select DIP Switch S1 Mode DIP Switch SW1 Active-High 24FPGA Mode DIP Switch SW1 Vita 57.1 FMC LPC Connector 28VITA 57.1 FMC LPC Connections LPC Pin Power Management AC Adapter and 12V Input Power Jack/Switch Onboard Power Regulation Power Management UCD9240PFC 30SP605 Fpga Configuration Modes M10 Bus Width Configuration OptionsConfiguration Solution User Guide Section SP605 Evaluation Board Table A-1Default Switch Settings Function/Type Default FMC Jtag Vita 57.1 FMC LPC Connector Pinout Appendix B Vita 57.1 FMC LPC Connector Pinout SP605 Master UCF Appendix C SP605 Master UCF NET Fmcpwrgoodflashrstb NET Fpgacmpcsb NET MEM1LDQSN LOC NET Sysclkn Appendix C SP605 Master UCF References