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Xilinx Power Management, AC Adapter and 12V Input Power Jack/Switch, SP605 Evaluation Board

Models: SP605

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Table 1-28:VITA 57.1 FMC LPC Connections (Cont’d)

Chapter 1: SP605 Evaluation Board

Table 1-28:VITA 57.1 FMC LPC Connections (Cont’d)

J63 FMC	Schematic Net Name	U1 FPGA		J63 FMC	Schematic Net Name	U1 FPGA
LPC Pin	Schematic Net Name	Pin		LPC Pin	Schematic Net Name	Pin
LPC Pin		Pin		LPC Pin		Pin

G21	FMC_LA20_P	R9		H20	FMC_LA15_N	D19

G22	FMC_LA20_N	R8		H22	FMC_LA19_P	R11

G24	FMC_LA22_P	V7		H23	FMC_LA19_N	T11

G25	FMC_LA22_N	W8		H25	FMC_LA21_P	V11

G27	FMC_LA25_P	W14		H26	FMC_LA21_N	W11

G28	FMC_LA25_N	Y14		H28	FMC_LA24_P	AA14

G30	FMC_LA29_P	T15		H29	FMC_LA24_N	AB14

G31	FMC_LA29_N	U15		H31	FMC_LA28_P	AA16

G33	FMC_LA31_P	U16		H32	FMC_LA28_N	AB16

G34	FMC_LA31_N	V15		H34	FMC_LA30_P	Y15

G36	FMC_LA33_P	Y17		H35	FMC_LA30_N	AB15

G37	FMC_LA33_N	AB17		H37	FMC_LA32_P	W17

				H38	FMC_LA32_N	Y18

Power Management

AC Adapter and 12V Input Power Jack/Switch

The SP605 is powered from a 12V source that is connected through a 6-pin (2X3) right angle Mini-Fit type connector J18. The AC-to-DC power supply included in the kit has a mating 6-pin plug.

When the SP605 is installed into a table top or tower PC's PCIe slot, the SP605 is typically powered from the PC ATX power supply. One of the PCs ATX hard disk type 4-pin power connectors is plugged into SP605 connector J27. The SP605 can be powered with the AC power adapter (plugged into J18) even when plugged into a PC PCIe motherboard slot; however, users are cautioned not to also connect a PC ATX type 4-pin power connector to J27. See the caution notes below and in Figure 1-20, page 46.

Caution! Caution! DO NOT plug a PC ATX power supply 6-pin connector into SP605 connector J18.The ATX 6-pin connector has a different pinout than SP605 J18, and connecting the ATX 6-pin connector will damage the SP605 and void the board warranty.

Caution! DO NOT apply power to 6-pin Mini-Fit type connector J18 and 4-pin ATX disk drive type connector J27 at the same time as this will damage the SP605 board. Refer to Figure 1-20, page 46 for details. The SP605 Power can be turned on or off through the board mounted slide switch SW2. When the switch is in the on position, a green LED (DS14) is illuminated.

52	www.xilinx.com	SP605 Hardware User Guide
		UG526 (v1.1.1) February 1, 2010

Image 52

Xilinx SP605 manual Power Management, AC Adapter and 12V Input Power Jack/Switch, 28 VITA 57.1 FMC LPC Connections Cont’d

Contents

SP605 Hardware User Guide UG526 v1.1.1 February 1, 2010 optionalGuide Subtitle optional Updated Figure 1-17 and Figure Revision HistoryDate VersionPreface About This Guide Table of ContentsChapter 1 SP605 Evaluation Board Appendix A Default Jumper and Switch Settings Appendix B VITA 57.1 FMC LPC Connector PinoutAppendix C SP605 Master UCF Appendix D References Mode DIP Switch SW1 Active-High 18. VITA 57.1 FMC LPC ConnectorGuide Contents Appendix A, “Default Jumper and Switch Settings.”Appendix B, “VITA 57.1 FMC LPC Connector Pinout.” About This GuideAdditional Support Resources Preface About This GuideSP605 Evaluation Board ChapterOverview Additional InformationFeatures 5. System ACE CF and CompactFlash Connector 6. USB JTAG10. SFP Module Connector 11. 10/100/1000 Tri-Speed Ethernet PHY Chapter 1 SP605 Evaluation BoardBlock Diagram 17. Switches18. VITA 57.1 FMC LPC Connector Configuration Options 4. Linear BPI Flash 5. System ACE CF and CompactFlash ConnectorSP605 Features FeatureRelated Xilinx Documents Detailed DescriptionSP605 Features Cont’d Detailed DescriptionFeature Linear BPI FlashConfiguration 1. Spartan-6 XC6SLX45T-3FGG484 FPGAReferences SP605 Features Cont’dSignal Name 2. 128 MB DDR3 Component MemoryI/O Voltage Rails Table 1-2 I/O Voltage Rail of FPGA BanksSchematic Net Name Table 1-4 FPGA On-Chip OCT Termination External Resistor RequirementsU1 FPGA Pin FPGA Pin NumberDDR3 Component Memory Connections Cont’d ReferencesDetailed Description Memory U423. SPI x4 Flash SilkscreenFigure 1-3 J17 SPI Flash Programming Header Figure 1-4 SPI Flash Interface TopologyDetailed Description Table 1-6 SPI x4 Memory Connections SPI MEM U32SPI HDR J17 Schematic Net Name4. Linear BPI Flash Figure 1-5 Linear BPI Flash InterfaceTable 1-7 Linear Flash Connections U25 BPI FLASHDetailed Description Table 1-7 Linear Flash Connections Cont’d Schematic Net NameU1 FPGA Pin U25 BPI FLASH5. System ACE CF and CompactFlash Connector FPGA Design Considerations for the Configuration FlashReferences Chapter 1 SP605 Evaluation BoardSchematic Net Name1 Table 1-8 System ACE CF ConnectionsU17 XCCACETQ144I Detailed DescriptionFigure 1-6 JTAG Chain Diagram 6. USB JTAGTable 1-8 System ACE CF Connections Cont’d Schematic Net Name7. Clock Generation Oscillator DifferentialFigure 1-7 VITA 57.1 FMC LPC J2 JTAG Bypass Jumper J19 ReferencesOscillator Socket Single-Ended, 2.5V or Figure 1-8 SP605 X2 Oscillator Socket Pin 1 Location IdentifiersFigure 1-9 SP605 X2 Oscillator Pin 1 Location Identifiers Silkscreened outline has beveled corner Socket has notch in crossbarSMA Connectors Differential 8. Multi-Gigabit Transceivers GTP MGTsTable 1-9 SP605 Clock Source Connections SourceFigure 1-10 GTP SMA Clock SMA MGT ConnectorsMGT REFCLK Chapter 1 SP605 Evaluation BoardDetailed Description Table 1-10 GTP SMA Clock Connections SMA PinSchematic Net Name U1 FPGA PinTable 1-11 PCIe Edge Connector Connections P4 PCIe Edge Connector9. PCI Express Endpoint Connectivity Chapter 1 SP605 Evaluation BoardDetailed Description ReferencesProduct information 10. SFP Module Connector SFP Control/Status SignalP2 SFP Module Connector Table 1-12 SFP Module Control and StatusTable 1-14 PHY Configuration Pins 11. 10/100/1000 Tri-Speed Ethernet PHYBit2 Bit1Table 1-15 Ethernet PHY Connections Cont’d ReferencesChapter 1 SP605 Evaluation Board U1 FPGA PinTable 1-16 USB Type B Pin Assignments and Signal Definitions USB Connector12. USB-to-UART Bridge DescriptionSchematic Net 13. DVI CODECTable 1-18 DVI Controller Connections U31 Chrontel CH7301CFigure 1-11 IIC Bus Topology 14. IIC BusDetailed Description Schematic External Access8-Kb NV Memory Table 1-19 IIC Bus ConnectionsSchematic Netname Detailed Description Table 1-20 IIC Memory ConnectionsIIC Memory U4 References15. Status LEDs Table 1-21 Status LEDsColor LabelDirection Indicator DUP TX RX Ethernet PHY Status LEDsLink Rate Mbps 100 1000 P1FPGA INIT and DONE LEDs VCC2V5FPGAINITB FPGADONEUser LEDs User Pushbutton Switches User DIP Switch User SIP Header 16. User I/OUser LEDs User SMA GPIOUser Pushbutton Switches Figure 1-16 User Pushbutton Switch TypicalTable 1-24 Pushbutton Switch Connections Switch PinUser DIP Switch Figure 1-17 User DIP Switch S2 Table 1-25 User DIP Switch ConnectionsDIP Switch Pin Schematic Net NameUser SIP Header Figure 1-18 User SIP Header J55Table 1-26 User SIP Header Connections Schematic Net NameUser SMA GPIO Figure 1-19 User SMA GPIOTable 1-27 User SMA Connections GPIO SMA Pin17. Switches Power On/Off Slide Switch SW2Power On/Off Slide Switch SW2 FPGAPROGB Pushbutton SW3 Active-Low SYSACERESETB Pushbutton SW9 Active-LowSYSACERESETB Pushbutton SW9 Active-Low Figure 1-22 System ACE CF RESETB Pushbutton SW9FPGAPROGB Pushbutton SW3 Active-Low Figure 1-21 FPGA PROGB Pushbutton SW3System ACE CF CompactFlash Image Select DIP Switch S1 Active-High Figure 1-23 System ACE CF CompactFlash Image Select DIP Switch S1SDMX-4-X Chapter 1 SP605 Evaluation BoardMode DIP Switch SW1 Active-High Figure 1-24 FPGA Mode DIP Switch SW1R9 SDMX-2-X References18. VITA 57.1 FMC LPC Connector Chapter 1 SP605 Evaluation BoardTable 1-28 VITA 57.1 FMC LPC Connections J63 FMCLPC Pin Appendix B, “VITA 57.1 FMC LPC Connector Pinout.”Power Management AC Adapter and 12V Input Power Jack/SwitchTable 1-28 VITA 57.1 FMC LPC Connections Cont’d Schematic Net NameOnboard Power Regulation Power ManagementPower Supply Figure 1-25 Onboard Power RegulatorsTable 1-29 Onboard Power System Devices Power Rail NetDevice Type ReferenceConfiguration Options Configuration Options“5. System ACE CF and CompactFlash Connector,” page Table 1-30 SP605 FPGA Configuration ModesSP605 Hardware User Guide Chapter 1 SP605 Evaluation BoardUG526 v1.1.1 February 1 Default Jumper and Switch Settings Table A-1 Default Switch SettingsDefault Appendix AAppendix A Default Jumper and Switch Settings Table A-2 Default Jumper SettingsCF Error LED JumperVITA 57.1 FMC LPC Connector Pinout Figure B-1 FMC LPC Connector PinoutAppendix B UG526 v1.1.1 February 1SP605 Hardware User Guide Appendix B VITA 57.1 FMC LPC Connector PinoutUG526 v1.1.1 February 1 Appendix C SP605 Master UCFUG526 v1.1.1 February 1 SP605 Hardware User Guide Appendix C SP605 Master UCFUG526 v1.1.1 February 1 UG526 v1.1.1 February 1 LOC = AA20Appendix C SP605 Master UCF 3. Series resistors are included SP605 Hardware User Guide Appendix C SP605 Master UCFUG526 v1.1.1 February 1 References Appendix D